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| author | Eric Auger <eric.auger@redhat.com> | 2020-07-28 17:08:15 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-08-24 10:02:06 +0100 |
| commit | de206dfd80412ed1cdfb70d43ad53c59a19361ab (patch) | |
| tree | 9701cb7a6c4ac5fbed439e55f455c4c3be68db9f | |
| parent | e7c3b9d9a0ddee7daa9b08bd14bd3ebbcf5f5cd3 (diff) | |
| download | qemu-de206dfd80412ed1cdfb70d43ad53c59a19361ab.zip qemu-de206dfd80412ed1cdfb70d43ad53c59a19361ab.tar.gz qemu-de206dfd80412ed1cdfb70d43ad53c59a19361ab.tar.bz2 | |
hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation
Expose the RIL bit so that the guest driver uses range
invalidation. Although RIL is a 3.2 features, We let
the AIDR advertise SMMUv3.1 support as v3.x implementation
is allowed to implement features from v3.(x+1).
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-12-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/arm/smmuv3-internal.h | 1 | ||||
| -rw-r--r-- | hw/arm/smmuv3.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 9ae7d97..fa3c088 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -55,6 +55,7 @@ REG32(IDR1, 0x4) REG32(IDR2, 0x8) REG32(IDR3, 0xc) FIELD(IDR3, HAD, 2, 1); + FIELD(IDR3, RIL, 10, 1); REG32(IDR4, 0x10) REG32(IDR5, 0x14) FIELD(IDR5, OAS, 0, 3); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index b262f0e..0122700 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -254,6 +254,7 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1); /* 4K and 64K granule support */ |