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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-09-15 17:23:47 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-11-07 13:08:48 +0100 |
| commit | c61b18a5d0562851b933cd2fdc61cf21ea1be270 (patch) | |
| tree | 0322b6fa6a889b52fc6460c77827d8ae2aa9d718 | |
| parent | 571568a173dfae14c27ef0db9fd2f7b77f0e4bad (diff) | |
| download | qemu-c61b18a5d0562851b933cd2fdc61cf21ea1be270.zip qemu-c61b18a5d0562851b933cd2fdc61cf21ea1be270.tar.gz qemu-c61b18a5d0562851b933cd2fdc61cf21ea1be270.tar.bz2 | |
target/nios2: Create IRQs *after* accelerator vCPU is realized
Architecture specific hardware doesn't have a particular dependency
on the accelerator vCPU (created with cpu_exec_realizefn), and can
be initialized *after* the vCPU is realized. Doing so allows further
generic API simplification (in few commits).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230918160257.30127-12-philmd@linaro.org>
| -rw-r--r-- | target/nios2/cpu.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 15e499f..a27732b 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -199,14 +199,6 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev); Error *local_err = NULL; -#ifndef CONFIG_USER_ONLY - if (cpu->eic_present) { - qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); - } else { - qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); - } -#endif - cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -220,6 +212,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) /* We have reserved storage for cpuid; might as well use it. */ cpu->env.ctrl[CR_CPUID] = cs->cpu_index; +#ifndef CONFIG_USER_ONLY + if (cpu->eic_present) { + qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); + } else { + qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); + } +#endif + ncc->parent_realize(dev, errp); } |