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authorRichard Henderson <richard.henderson@linaro.org>2023-03-20 09:36:31 -0700
committerRichard Henderson <richard.henderson@linaro.org>2023-05-16 20:13:51 -0700
commitc60ad6e3b9be0c9622811715ffdd921bfd6ea7d2 (patch)
tree94d9bfdcce9f6ce89edb849d0688dd593274221e
parentb2485530d8873f8c3a4f32bf718a52527e7d2981 (diff)
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tcg/i386: Adjust type of tlb_mask
Because of its use on tgen_arithi, this value must be a signed 32-bit quantity, as that is what may be encoded in the insn. The truncation of the value to unsigned for 32-bit guests is done via the REX bit via 'trexw'. Removes the only uses of target_ulong from this tcg backend. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--tcg/i386/tcg-target.c.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 5d7fe5b..d85f980 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -1920,7 +1920,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
unsigned mem_index = get_mmuidx(oi);
unsigned s_bits = opc & MO_SIZE;
unsigned s_mask = (1 << s_bits) - 1;
- target_ulong tlb_mask;
+ int tlb_mask;
ldst = new_ldst_label(s);
ldst->is_ld = is_ld;
@@ -1965,7 +1965,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
addrlo, s_mask - a_mask);
}
- tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
+ tlb_mask = TARGET_PAGE_MASK | a_mask;
tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
/* cmp 0(TCG_REG_L0), TCG_REG_L1 */