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| author | Richard Henderson <rth@twiddle.net> | 2012-08-17 11:20:33 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-01-05 12:00:28 -0800 |
| commit | ade9dea429e202eabf87a36a20d1d3bbc34d8910 (patch) | |
| tree | 7fd0bd46292778bdfc1a16881ccf13f1f3ad900f | |
| parent | 11bf2d73d0dba509e14dbfc2189365410a5a2c06 (diff) | |
| download | qemu-ade9dea429e202eabf87a36a20d1d3bbc34d8910.zip qemu-ade9dea429e202eabf87a36a20d1d3bbc34d8910.tar.gz qemu-ade9dea429e202eabf87a36a20d1d3bbc34d8910.tar.bz2 | |
target-s390: Convert LOAD LOGICAL IMMEDIATE
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target-s390x/insn-data.def | 7 | ||||
| -rw-r--r-- | target-s390x/translate.c | 42 |
2 files changed, 19 insertions, 30 deletions
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 7a8dcbd..89bc635 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -168,6 +168,13 @@ /* LOAD LOGICAL HALFWORD RELATIVE LONG */ C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0) C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0) +/* LOAD LOGICAL IMMEDATE */ + D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32) + D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0) + D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48) + D(0xa50d, LLIHL, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 32) + D(0xa50e, LLILH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 16) + D(0xa50f, LLILL, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 0) /* MULTIPLY */ C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 9239025..0143758 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2033,26 +2033,6 @@ static void disas_a5(CPUS390XState *env, DisasContext *s, int op, int r1, tcg_temp_free_i32(tmp32); tcg_temp_free_i64(tmp); break; - case 0xc: /* LLIHH R1,I2 [RI] */ - tmp = tcg_const_i64( ((uint64_t)i2) << 48 ); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; - case 0xd: /* LLIHL R1,I2 [RI] */ - tmp = tcg_const_i64( ((uint64_t)i2) << 32 ); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; - case 0xe: /* LLILH R1,I2 [RI] */ - tmp = tcg_const_i64( ((uint64_t)i2) << 16 ); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; - case 0xf: /* LLILL R1,I2 [RI] */ - tmp = tcg_const_i64(i2); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; default: LOG_DISAS("illegal a5 operation 0x%x\n", op); gen_illegal_opcode(s); @@ -3043,16 +3023,6 @@ static void disas_c0(CPUS390XState *env, DisasContext *s, int op, int r1, int i2 tcg_temp_free_i64(tmp); tcg_temp_free_i32(tmp32_1); break; - case 0xe: /* LLIHF R1,I2 [RIL] */ - tmp = tcg_const_i64(((uint64_t)(uint32_t)i2) << 32); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; - case 0xf: /* LLILF R1,I2 [RIL] */ - tmp = tcg_const_i64((uint32_t)i2); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; default: LOG_DISAS("illegal c0 operation 0x%x\n", op); gen_illegal_opcode(s); @@ -4694,6 +4664,18 @@ static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o) o->in2 = tcg_const_i64((uint32_t)get_field(f, i2)); } +static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o) +{ + uint64_t i2 = (uint16_t)get_field(f, i2); + o->in2 = tcg_const_i64(i2 << s->insn->data); +} + +static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o) +{ + uint64_t i2 = (uint32_t)get_field(f, i2); + o->in2 = tcg_const_i64(i2 << s->insn->data); +} + /* ====================================================================== */ /* Find opc within the table of insns. This is formulated as a switch |