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| author | Song Gao <gaosong@loongson.cn> | 2023-09-14 10:26:33 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-09-20 14:33:41 +0800 |
| commit | abee168ea3bde3be1570cc23e3b3b3138783479d (patch) | |
| tree | ab1381bc398f0899cedf75354936a7fc7cfdeb6b | |
| parent | 1b3e242f72c5b4cca00309f1cf644a019a24c784 (diff) | |
| download | qemu-abee168ea3bde3be1570cc23e3b3b3138783479d.zip qemu-abee168ea3bde3be1570cc23e3b3b3138783479d.tar.gz qemu-abee168ea3bde3be1570cc23e3b3b3138783479d.tar.bz2 | |
target/loongarch: Implement xvfrstp
This patch includes:
- XVFRSTP[I].{B/H}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-46-gaosong@loongson.cn>
| -rw-r--r-- | target/loongarch/disas.c | 5 | ||||
| -rw-r--r-- | target/loongarch/insn_trans/trans_vec.c.inc | 4 | ||||
| -rw-r--r-- | target/loongarch/insns.decode | 5 | ||||
| -rw-r--r-- | target/loongarch/vec_helper.c | 32 |
4 files changed, 34 insertions, 12 deletions
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 7f04c91..1c4aeca 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -2235,6 +2235,11 @@ INSN_LASX(xvbitrevi_h, vv_i) INSN_LASX(xvbitrevi_w, vv_i) INSN_LASX(xvbitrevi_d, vv_i) +INSN_LASX(xvfrstp_b, vvv) +INSN_LASX(xvfrstp_h, vvv) +INSN_LASX(xvfrstpi_b, vv_i) +INSN_LASX(xvfrstpi_h, vv_i) + INSN_LASX(xvreplgr2vr_b, vr) INSN_LASX(xvreplgr2vr_h, vr) INSN_LASX(xvreplgr2vr_w, vr) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/trans_vec.c.inc index 9e7eb30..c1e7130 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -4300,6 +4300,10 @@ TRANS(vfrstp_b, LSX, gen_vvv, gen_helper_vfrstp_b) TRANS(vfrstp_h, LSX, gen_vvv, gen_helper_vfrstp_h) TRANS(vfrstpi_b, LSX, gen_vv_i, gen_helper_vfrstpi_b) TRANS(vfrstpi_h, LSX, gen_vv_i, gen_helper_vfrstpi_h) +TRANS(xvfrstp_b, LASX, gen_xxx, gen_helper_vfrstp_b) +TRANS(xvfrstp_h, LASX, gen_xxx, gen_helper_vfrstp_h) +TRANS(xvfrstpi_b, LASX, gen_xx_i, gen_helper_vfrstpi_b) +TRANS(xvfrstpi_h, LASX, gen_xx_i, gen_helper_vfrstpi_h) TRANS(vfadd_s, LSX, gen_vvv_ptr, gen_helper_vfadd_s) TRANS(vfadd_d, LSX, gen_vvv_ptr, gen_helper_vfadd_d) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index cb6db80..6035fe1 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1811,6 +1811,11 @@ xvbitrevi_h 0111 01110001 10000 1 .... ..... ..... @vv_ui4 xvbitrevi_w 0111 01110001 10001 ..... ..... ..... @vv_ui5 xvbitrevi_d 0111 01110001 1001 ...... ..... ..... @vv_ui6 +xvfrstp_b 0111 01010010 10110 ..... ..... ..... @vvv +xvfrstp_h 0111 01010010 10111 ..... ..... ..... @vvv +xvfrstpi_b 0111 01101001 10100 ..... ..... ..... @vv_ui5 +xvfrstpi_h 0111 01101001 10101 ..... ..... ..... @vv_ui5 + xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c index ec63efb..9ddbbc6 100644 --- a/target/loongarch/vec_helper.c +++ b/target/loongarch/vec_helper.c @@ -2369,18 +2369,22 @@ DO_BITI(vbitrevi_d, 64, UD, DO_BITREV) #define VFRSTP(NAME, BIT, MASK, E) \ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \ { \ - int i, m; \ + int i, j, m, ofs; \ VReg *Vd = (VReg *)vd; \ VReg *Vj = (VReg *)vj; \ VReg *Vk = (VReg *)vk; \ + int oprsz = simd_oprsz(desc); \ \ - for (i = 0; i < LSX_LEN/BIT; i++) { \ - if (Vj->E(i) < 0) { \ - break; \ + ofs = LSX_LEN / BIT; \ + for (i = 0; i < oprsz / 16; i++) { \ + m = Vk->E(i * ofs) & MASK; \ + for (j = 0; j < ofs; j++) { \ + if (Vj->E(j + ofs * i) < 0) { \ + break; \ + } \ } \ + Vd->E(m + i * ofs) = j; \ } \ - m = Vk->E(0) & MASK; \ - Vd->E(m) = i; \ } VFRSTP(vfrstp_b, 8, 0xf, B) @@ -2389,17 +2393,21 @@ VFRSTP(vfrstp_h, 16, 0x7, H) #define VFRSTPI(NAME, BIT, E) \ void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ { \ - int i, m; \ + int i, j, m, ofs; \ VReg *Vd = (VReg *)vd; \ VReg *Vj = (VReg *)vj; \ + int oprsz = simd_oprsz(desc); \ \ - for (i = 0; i < LSX_LEN/BIT; i++) { \ - if (Vj->E(i) < 0) { \ - break; \ + ofs = LSX_LEN / BIT; \ + m = imm % ofs; \ + for (i = 0; i < oprsz / 16; i++) { \ + for (j = 0; j < ofs; j++) { \ + if (Vj->E(j + ofs * i) < 0) { \ + break; \ + } \ } \ + Vd->E(m + i * ofs) = j; \ } \ - m = imm % (LSX_LEN/BIT); \ - Vd->E(m) = i; \ } VFRSTPI(vfrstpi_b, 8, B) |