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| author | Jiaxi Chen <jiaxi.chen@linux.intel.com> | 2023-03-03 14:59:10 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-04-28 12:50:34 +0200 |
| commit | a957a88416ecbec51e147cba9fe89b93f6646b3b (patch) | |
| tree | 7f434219eb21bf65e9b5765a41f9c5ef51f4fe1e | |
| parent | 99ed8445ea27742a4df40f51a3a5fbd6f8e76fa5 (diff) | |
| download | qemu-a957a88416ecbec51e147cba9fe89b93f6646b3b.zip qemu-a957a88416ecbec51e147cba9fe89b93f6646b3b.tar.gz qemu-a957a88416ecbec51e147cba9fe89b93f6646b3b.tar.bz2 | |
target/i386: Add support for AVX-IFMA in CPUID enumeration
AVX-IFMA is a new instruction in the latest Intel platform Sierra
Forest. This instruction packed multiplies unsigned 52-bit integers and
adds the low/high 52-bit products to Qword Accumulators.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 23]
Add CPUID definition for AVX-IFMA.
Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20230303065913.1246327-4-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 841c407..8eb2ee5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -879,7 +879,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, "fzrm", "fsrs", "fsrc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, "amx-fp16", NULL, NULL, + NULL, "amx-fp16", NULL, "avx-ifma", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7deb37e..1f72d11 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -917,6 +917,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_7_1_EAX_FSRC (1U << 12) /* Support Tile Computational Operations on FP16 Numbers */ #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) +/* Support for VPMADD52[H,L]UQ */ +#define CPUID_7_1_EAX_AVX_IFMA (1U << 23) /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) |