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| author | Changbin Du <changbin.du@gmail.com> | 2021-05-19 23:57:38 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-06-08 09:59:43 +1000 |
| commit | a722701dd364b82dc115e94a29d767949f796000 (patch) | |
| tree | 2bdf95a6aeba4113b53f6dc525cfd94724aef4ad | |
| parent | 9a575d33fba497db48cda36273bde8710651888e (diff) | |
| download | qemu-a722701dd364b82dc115e94a29d767949f796000.zip qemu-a722701dd364b82dc115e94a29d767949f796000.tar.gz qemu-a722701dd364b82dc115e94a29d767949f796000.tar.bz2 | |
target/riscv: Dump CSR mscratch/sscratch/satp
This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
the output of CSR mtval/stval.
Signed-off-by: Changbin Du <changbin.du@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210519155738.20486-1-changbin.du@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index aa48bca..ee2523f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -286,12 +286,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); } + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); #endif for (i = 0; i < 32; i++) { |