diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-02 10:07:57 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-05-16 20:13:51 -0700 |
| commit | a66efde188e43041277822e582de1c897b966792 (patch) | |
| tree | e88b456e2e91beb12dd301234be77969c3508f6a | |
| parent | aece72b76bfeffcab715cd62742fd7f366ceb079 (diff) | |
| download | qemu-a66efde188e43041277822e582de1c897b966792.zip qemu-a66efde188e43041277822e582de1c897b966792.tar.gz qemu-a66efde188e43041277822e582de1c897b966792.tar.bz2 | |
tcg: Add tlb_dyn_max_bits to TCGContext
Disconnect guest tlb parameters from TCG compilation.
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | accel/tcg/translate-all.c | 1 | ||||
| -rw-r--r-- | include/tcg/tcg.h | 1 | ||||
| -rw-r--r-- | tcg/aarch64/tcg-target.c.inc | 2 | ||||
| -rw-r--r-- | tcg/i386/tcg-target.c.inc | 2 |
4 files changed, 4 insertions, 2 deletions
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ca306f6..353849c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -360,6 +360,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, #ifdef CONFIG_SOFTMMU tcg_ctx->page_bits = TARGET_PAGE_BITS; tcg_ctx->page_mask = TARGET_PAGE_MASK; + tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS; #endif tb_overflow: diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index db57c4d..cd6327b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -563,6 +563,7 @@ struct TCGContext { #ifdef CONFIG_SOFTMMU int page_mask; uint8_t page_bits; + uint8_t tlb_dyn_max_bits; #endif TCGRegSet reserved_regs; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index c2a1f09..bc6b99a 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1663,7 +1663,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ldst->oi = oi; ldst->addrlo_reg = addr_reg; - mask_type = (s->page_bits + CPU_TLB_DYN_MAX_BITS > 32 + mask_type = (s->page_bits + s->tlb_dyn_max_bits > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index c5d4570..8b9a5f0 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1933,7 +1933,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW); if (TCG_TYPE_PTR == TCG_TYPE_I64) { hrexw = P_REXW; - if (s->page_bits + CPU_TLB_DYN_MAX_BITS > 32) { + if (s->page_bits + s->tlb_dyn_max_bits > 32) { tlbtype = TCG_TYPE_I64; tlbrexw = P_REXW; } |