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| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-04-20 08:56:15 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-04-26 23:02:42 +0200 |
| commit | 9c2627b09d1bdee8a58730bbf48c76be48bd659f (patch) | |
| tree | a40a979f0554af1cb75ddf40f0228c3e78486085 | |
| parent | 88770fec6c8daeb96c1f5cdbedff9df173431fd6 (diff) | |
| download | qemu-9c2627b09d1bdee8a58730bbf48c76be48bd659f.zip qemu-9c2627b09d1bdee8a58730bbf48c76be48bd659f.tar.gz qemu-9c2627b09d1bdee8a58730bbf48c76be48bd659f.tar.bz2 | |
target-ppc: add instruction flags for Book I 2.05
.. and enable it on POWER7 CPU.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target-ppc/cpu.h | 4 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index b8b09b9..7cacb56 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1870,8 +1870,10 @@ enum { PPC2_PRCNTL = 0x0000000000000008ULL, /* Byte-reversed, indexed, double-word load and store */ PPC2_DBRX = 0x0000000000000010ULL, + /* Book I 2.05 PowerPC specification */ + PPC2_ISA205 = 0x0000000000000020ULL, -#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX) +#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX | PPC2_ISA205) }; /*****************************************************************************/ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index b0e3536..6feb62a 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7042,7 +7042,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC_64B | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; - pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX; + pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205; pcc->msr_mask = 0x800000000204FF36ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) |