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| author | Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 2020-11-18 17:04:14 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-11-23 10:41:58 +0000 |
| commit | 98e8779770c40901ed585745aacc9a8e2b934a28 (patch) | |
| tree | 802d8ea88705340c06e8d2715866d38ae831bb97 | |
| parent | 8cc30eb1400fc01f2b139cdd3dc524f8b84dbe07 (diff) | |
| download | qemu-98e8779770c40901ed585745aacc9a8e2b934a28.zip qemu-98e8779770c40901ed585745aacc9a8e2b934a28.tar.gz qemu-98e8779770c40901ed585745aacc9a8e2b934a28.tar.bz2 | |
target/arm: fix stage 2 page-walks in 32-bit emulation
Using a target unsigned long would limit the Input Address to a LPAE
page-walk to 32 bits on AArch32 and 64 bits on AArch64. This is okay
for stage 1 or on AArch64, but it is insufficient for stage 2 on
AArch32. In that later case, the Input Address can have up to 40 bits.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201118150414.18360-1-remi@remlab.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 11b0803..38cd35c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -40,7 +40,7 @@ #ifndef CONFIG_USER_ONLY -static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, +static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool s1_is_el0, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, @@ -10988,7 +10988,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, * @fi: set to fault info if the translation fails * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes */ -static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, +static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool s1_is_el0, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |