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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-07-23 17:21:45 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-07-27 10:57:39 +0100 |
| commit | 7caad65756c0afaf4b238b068ab61481eb68a1dc (patch) | |
| tree | 3867aea2a0de36d6596ead7eea4585261efcfa3c | |
| parent | 41487794f5af977e992870e18521bed88daa68d5 (diff) | |
| download | qemu-7caad65756c0afaf4b238b068ab61481eb68a1dc.zip qemu-7caad65756c0afaf4b238b068ab61481eb68a1dc.tar.gz qemu-7caad65756c0afaf4b238b068ab61481eb68a1dc.tar.bz2 | |
hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of
the register. We were incorrectly masking it to 8 bits, so it would
report the wrong value if the pending exception was greater than 256.
Fix the bug.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-6-peter.maydell@linaro.org
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2aba213..c9149a3 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1039,7 +1039,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) /* VECTACTIVE */ val = cpu->env.v7m.exception; /* VECTPENDING */ - val |= (s->vectpending & 0xff) << 12; + val |= (s->vectpending & 0x1ff) << 12; /* ISRPENDING - set if any external IRQ is pending */ if (nvic_isrpending(s)) { val |= (1 << 22); |