diff options
| author | Max Chou <max.chou@sifive.com> | 2023-10-26 23:18:08 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:06:02 +1000 |
| commit | 5ddbc83ff2f830f2e96c933d78ccf59c1507eab6 (patch) | |
| tree | 6d355aaf09e7396cdc430a06f1dedc0b148a00e7 | |
| parent | c0ce1f2a88c7fb7c923e1764d7af53f4cc815486 (diff) | |
| download | qemu-5ddbc83ff2f830f2e96c933d78ccf59c1507eab6.zip qemu-5ddbc83ff2f830f2e96c933d78ccf59c1507eab6.tar.gz qemu-5ddbc83ff2f830f2e96c933d78ccf59c1507eab6.tar.bz2 | |
target/riscv: Add cfg property for Zvkt extension
Vector crypto spec defines the Zvkt extension that included all of the
instructions of Zvbb & Zvbc extensions and some vector instructions.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu_cfg.h | 1 | ||||
| -rw-r--r-- | target/riscv/tcg/tcg-cpu.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 6eef4a5..1f0dac5 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -96,6 +96,7 @@ struct RISCVCPUConfig { bool ext_zvknhb; bool ext_zvksed; bool ext_zvksh; + bool ext_zvkt; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 093bda2..87baae5 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -499,6 +499,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (cpu->cfg.ext_zvkt) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); + } + /* * In principle Zve*x would also suffice here, were they supported * in qemu |