diff options
| author | Matheus Ferst <matheus.ferst@eldorado.org.br> | 2022-03-14 15:57:17 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-03-14 15:57:17 +0100 |
| commit | 52d324ff13fcf97bc31f2e24803e366d330aa7cc (patch) | |
| tree | 58fbe26593e6b80df3fdfbca6277b3cc12001a86 | |
| parent | c6242335b3ff504a552ceba18c8b8ab9dc684a77 (diff) | |
| download | qemu-52d324ff13fcf97bc31f2e24803e366d330aa7cc.zip qemu-52d324ff13fcf97bc31f2e24803e366d330aa7cc.tar.gz qemu-52d324ff13fcf97bc31f2e24803e366d330aa7cc.tar.bz2 | |
target/ppc: fix xxspltw for big endian hosts
Fix a typo in the host endianness macro and add a simple test to detect
regressions.
Fixes: 9bb0048ec6f8 ("target/ppc: convert xxspltw to vector operations")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220310172047.61094-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| -rw-r--r-- | target/ppc/translate/vsx-impl.c.inc | 2 | ||||
| -rw-r--r-- | tests/tcg/ppc64/Makefile.target | 1 | ||||
| -rw-r--r-- | tests/tcg/ppc64le/Makefile.target | 1 | ||||
| -rw-r--r-- | tests/tcg/ppc64le/xxspltw.c | 46 |
4 files changed, 49 insertions, 1 deletions
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index 48a97b2..e67fbf2 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1552,7 +1552,7 @@ static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2_uim2 *a) tofs = vsr_full_offset(a->xt); bofs = vsr_full_offset(a->xb); bofs += a->uim << MO_32; -#ifndef HOST_WORDS_BIG_ENDIAN +#ifndef HOST_WORDS_BIGENDIAN bofs ^= 8 | 4; #endif diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target index c949805..8197c28 100644 --- a/tests/tcg/ppc64/Makefile.target +++ b/tests/tcg/ppc64/Makefile.target @@ -27,5 +27,6 @@ run-sha512-vector: QEMU_OPTS+=-cpu POWER10 run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10 PPC64_TESTS += signal_save_restore_xer +PPC64_TESTS += xxspltw TESTS += $(PPC64_TESTS) diff --git a/tests/tcg/ppc64le/Makefile.target b/tests/tcg/ppc64le/Makefile.target index 12d85e9..9624bb1 100644 --- a/tests/tcg/ppc64le/Makefile.target +++ b/tests/tcg/ppc64le/Makefile.target @@ -25,5 +25,6 @@ run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10 PPC64LE_TESTS += mtfsf PPC64LE_TESTS += signal_save_restore_xer +PPC64LE_TESTS += xxspltw TESTS += $(PPC64LE_TESTS) diff --git a/tests/tcg/ppc64le/xxspltw.c b/tests/tcg/ppc64le/xxspltw.c new file mode 100644 index 0000000..4cff78b --- /dev/null +++ b/tests/tcg/ppc64le/xxspltw.c @@ -0,0 +1,46 @@ +#include <stdio.h> +#include <stdint.h> +#include <inttypes.h> +#include <assert.h> + +#define WORD_A 0xAAAAAAAAUL +#define WORD_B 0xBBBBBBBBUL +#define WORD_C 0xCCCCCCCCUL +#define WORD_D 0xDDDDDDDDUL + +#define DWORD_HI (WORD_A << 32 | WORD_B) +#define DWORD_LO (WORD_C << 32 | WORD_D) + +#define TEST(HI, LO, UIM, RES) \ + do { \ + union { \ + uint64_t u; \ + double f; \ + } h = { .u = HI }, l = { .u = LO }; \ + /* \ + * Use a pair of FPRs to load the VSR avoiding insns \ + * newer than xxswapd. \ + */ \ + asm("xxmrghd 32, %0, %1\n\t" \ + "xxspltw 32, 32, %2\n\t" \ + "xxmrghd %0, 32, %0\n\t" \ + "xxswapd 32, 32\n\t" \ + "xxmrghd %1, 32, %1\n\t" \ + : "+f" (h.f), "+f" (l.f) \ + : "i" (UIM) \ + : "v0"); \ + printf("xxspltw(0x%016" PRIx64 "%016" PRIx64 ", %d) =" \ + " %016" PRIx64 "%016" PRIx64 "\n", HI, LO, UIM, \ + h.u, l.u); \ + assert(h.u == (RES)); \ + assert(l.u == (RES)); \ + } while (0) + +int main(void) +{ + TEST(DWORD_HI, DWORD_LO, 0, WORD_A << 32 | WORD_A); + TEST(DWORD_HI, DWORD_LO, 1, WORD_B << 32 | WORD_B); + TEST(DWORD_HI, DWORD_LO, 2, WORD_C << 32 | WORD_C); + TEST(DWORD_HI, DWORD_LO, 3, WORD_D << 32 | WORD_D); + return 0; +} |