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authorRichard Henderson <richard.henderson@linaro.org>2022-06-01 18:33:56 -0700
committerLaurent Vivier <laurent@vivier.eu>2022-06-02 09:35:02 +0200
commit43accc4862e0a88710411b205fdaf833dadf9951 (patch)
treeaed5365e933e3702f68daec896f62649ce7c3555
parent815c6dea464c661032c6cc76f42160a6240c930e (diff)
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target/m68k: Implement TRAPV
Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-13-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
-rw-r--r--target/m68k/translate.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 8b2157c..0dfddaa 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -4910,6 +4910,14 @@ DISAS_INSN(trapcc)
do_trapcc(s, &c);
}
+DISAS_INSN(trapv)
+{
+ DisasCompare c;
+
+ gen_cc_cond(&c, s, 9); /* V set */
+ do_trapcc(s, &c);
+}
+
static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
{
switch (reg) {
@@ -6074,6 +6082,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(nop, 4e71, ffff);
INSN(rtd, 4e74, ffff, RTD);
BASE(rts, 4e75, ffff);
+ INSN(trapv, 4e76, ffff, M68000);
INSN(rtr, 4e77, ffff, M68000);
BASE(jump, 4e80, ffc0);
BASE(jump, 4ec0, ffc0);