aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAleksandar Markovic <amarkovic@wavecomp.com>2019-01-15 20:55:12 +0100
committerAleksandar Markovic <amarkovic@wavecomp.com>2019-01-18 16:53:28 +0100
commit3ef521ee9fe2d01d4bbcf3e4d5c91ed982bf3f60 (patch)
tree24083fab228c24c259f1739cef34a2e01ecb4805
parent04992c8cd1c43ecdba39dd8c916db092db6ebae0 (diff)
downloadqemu-3ef521ee9fe2d01d4bbcf3e4d5c91ed982bf3f60.zip
qemu-3ef521ee9fe2d01d4bbcf3e4d5c91ed982bf3f60.tar.gz
qemu-3ef521ee9fe2d01d4bbcf3e4d5c91ed982bf3f60.tar.bz2
target/mips: Add CP0 register MemoryMapID
Add CP0 register MemoryMapID. Only data field is added. The corresponding functionality will be added in future patches. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
-rw-r--r--target/mips/cpu.h1
-rw-r--r--target/mips/machine.c5
2 files changed, 4 insertions, 2 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a5381b7..21daf50 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -536,6 +536,7 @@ struct CPUMIPSState {
*/
target_ulong CP0_Context;
target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
+ int32_t CP0_MemoryMapID;
/*
* CP0 Register 5
*/
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 111d7c3..1341ab1 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 16,
- .minimum_version_id = 16,
+ .version_id = 17,
+ .minimum_version_id = 17,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -253,6 +253,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
+ VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),