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| author | Paolo Bonzini <pbonzini@redhat.com> | 2023-09-20 17:41:17 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-09-21 10:39:51 +0200 |
| commit | 0c49c9180c5498bcd55edc1bfb12b0466e08575c (patch) | |
| tree | 4ca1786729d1edf269be81774f2371970f09538a | |
| parent | 005ad32358f12fe9313a4a01918a55e60d4f39e5 (diff) | |
| download | qemu-0c49c9180c5498bcd55edc1bfb12b0466e08575c.zip qemu-0c49c9180c5498bcd55edc1bfb12b0466e08575c.tar.gz qemu-0c49c9180c5498bcd55edc1bfb12b0466e08575c.tar.bz2 | |
target/i386: enumerate bit 56 of MSR_IA32_VMX_BASIC
On parts that enumerate IA32_VMX_BASIC MSR bit as 1, any exception vector
can be delivered with or without an error code if the other consistency
checks are satisfied.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rwxr-xr-x | scripts/kvm/vmxcap | 1 | ||||
| -rw-r--r-- | target/i386/cpu.c | 1 | ||||
| -rw-r--r-- | target/i386/cpu.h | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/scripts/kvm/vmxcap b/scripts/kvm/vmxcap index ce27f5e..3fb4d5b 100755 --- a/scripts/kvm/vmxcap +++ b/scripts/kvm/vmxcap @@ -115,6 +115,7 @@ controls = [ (50, 53): 'VMCS memory type', 54: 'INS/OUTS instruction information', 55: 'IA32_VMX_TRUE_*_CTLS support', + 56: 'Skip checks on event error code', }, msr = MSR_IA32_VMX_BASIC, ), diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b2a2036..d48607b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1340,6 +1340,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .feat_names = { [54] = "vmx-ins-outs", [55] = "vmx-true-ctls", + [56] = "vmx-any-errcode", }, .msr = { .index = MSR_IA32_VMX_BASIC, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index fbb05ea..d1ffadd 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1039,6 +1039,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) +#define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56) #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) |