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| author | Victor CLEMENT <victor.clement@openwide.fr> | 2015-06-02 14:56:23 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-06-02 14:56:25 +0100 |
| commit | 0b2ff2ceb8a45cbe51ca13a1a32fc5bdeec71815 (patch) | |
| tree | 916e23e70af189de62e8ec74e4559a32234a8202 | |
| parent | bd204e63a7ce9d1b5c5903c9033863b179194989 (diff) | |
| download | qemu-0b2ff2ceb8a45cbe51ca13a1a32fc5bdeec71815.zip qemu-0b2ff2ceb8a45cbe51ca13a1a32fc5bdeec71815.tar.gz qemu-0b2ff2ceb8a45cbe51ca13a1a32fc5bdeec71815.tar.bz2 | |
pl061: fix wrong calculation of GPIOMIS register
The masked interrupt status register should be the state of the interrupt
after masking.
There should be a logical AND instead of a logical OR between the
interrupt status and the interrupt mask.
Signed-off-by: Victor CLEMENT <victor.clement@openwide.fr>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1433154824-6927-1-git-send-email-victor.clement@openwide.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/gpio/pl061.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index bd03e99..4ba730b 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -173,7 +173,7 @@ static uint64_t pl061_read(void *opaque, hwaddr offset, case 0x414: /* Raw interrupt status */ return s->istate; case 0x418: /* Masked interrupt status */ - return s->istate | s->im; + return s->istate & s->im; case 0x420: /* Alternate function select */ return s->afsel; case 0x500: /* 2mA drive */ |