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| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-02-02 13:04:26 +0100 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-02-08 09:58:08 +0100 |
| commit | fa581531ffdc94ba18da6ec0c566bece57a60a85 (patch) | |
| tree | 0ac4200794cba419db7a30139e92b6d0422f70e4 | |
| parent | 1c6b2e4b794d460a16a7f94cf6a7d6864f708be1 (diff) | |
| download | qemu-fa581531ffdc94ba18da6ec0c566bece57a60a85.zip qemu-fa581531ffdc94ba18da6ec0c566bece57a60a85.tar.gz qemu-fa581531ffdc94ba18da6ec0c566bece57a60a85.tar.bz2 | |
tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT
DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which
would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So
let's make each register unique.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-5-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| -rw-r--r-- | tests/tcg/tricore/Makefile.softmmu-target | 1 | ||||
| -rw-r--r-- | tests/tcg/tricore/macros.h | 16 | ||||
| -rw-r--r-- | tests/tcg/tricore/test_insert.S | 9 |
3 files changed, 22 insertions, 4 deletions
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target index bc0cfae..afabba8 100644 --- a/tests/tcg/tricore/Makefile.softmmu-target +++ b/tests/tcg/tricore/Makefile.softmmu-target @@ -11,6 +11,7 @@ TESTS += test_fadd.tst TESTS += test_fmul.tst TESTS += test_ftoi.tst TESTS += test_imask.tst +TESTS += test_insert.tst TESTS += test_madd.tst TESTS += test_msub.tst TESTS += test_muls.tst diff --git a/tests/tcg/tricore/macros.h b/tests/tcg/tricore/macros.h index ceb7e9c..4f2bc3c 100644 --- a/tests/tcg/tricore/macros.h +++ b/tests/tcg/tricore/macros.h @@ -9,10 +9,10 @@ /* Register definitions */ #define DREG_RS1 %d0 #define DREG_RS2 %d1 -#define DREG_RS3 %d4 -#define DREG_CALC_RESULT %d1 -#define DREG_CALC_PSW %d2 -#define DREG_CORRECT_PSW %d3 +#define DREG_RS3 %d2 +#define DREG_CALC_RESULT %d3 +#define DREG_CALC_PSW %d4 +#define DREG_CORRECT_PSW %d5 #define DREG_TEMP_LI %d10 #define DREG_TEMP %d11 #define DREG_TEST_NUM %d14 @@ -103,6 +103,14 @@ test_ ## num: \ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \ ) +#define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \ + TEST_CASE(num, DREG_CALC_RESULT, result, \ + LI(DREG_RS1, rs1); \ + LI(DREG_RS2, rs1); \ + rstv; \ + insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \ + ) + #define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \ TEST_CASE_E(num, res_lo, res_hi, \ LI(EREG_RS1_LO, rs1_lo); \ diff --git a/tests/tcg/tricore/test_insert.S b/tests/tcg/tricore/test_insert.S new file mode 100644 index 0000000..d5fd223 --- /dev/null +++ b/tests/tcg/tricore/test_insert.S @@ -0,0 +1,9 @@ +#include "macros.h" +.text +.global _start +_start: +# insn num result rs1 imm1 rs2 imm2 +# | | | | | | | + TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8) + + TEST_PASSFAIL |