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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-09-06 09:20:05 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-09-17 08:42:47 -0700 |
| commit | f3d47d580402d11b73108de807031124c135e370 (patch) | |
| tree | 9a5ee2ca12cd58f0a0c64669b8f6bfbf7585b7c1 | |
| parent | e8c56787cd78f5d26285120f85bf898f5d3693b9 (diff) | |
| download | qemu-f3d47d580402d11b73108de807031124c135e370.zip qemu-f3d47d580402d11b73108de807031124c135e370.tar.gz qemu-f3d47d580402d11b73108de807031124c135e370.tar.bz2 | |
riscv: sifive_u: Set the minimum number of cpus to 2
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
[Palmer: Set default CPUs to 2]
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| -rw-r--r-- | hw/riscv/sifive_u.c | 5 | ||||
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2947e06..feee21e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -10,7 +10,8 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * - * This board currently uses a hardcoded devicetree that indicates one hart. + * This board currently generates devicetree dynamically that indicates at least + * two harts. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -433,6 +434,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc) * management CPU. */ mc->max_cpus = 4; + mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus = mc->min_cpus; } DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index f25bad8..6d22741 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -69,6 +69,8 @@ enum { SIFIVE_U_GEM_CLOCK_FREQ = 125000000 }; +#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 + #define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_NUM_SOURCES 54 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 |