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| author | Richard Henderson <rth@twiddle.net> | 2012-08-22 11:24:25 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-01-05 12:18:39 -0800 |
| commit | eb66e6a96904e50a9d0d1a76aecfe8675f4d8673 (patch) | |
| tree | f00552140ea18f67fa72535597d75e5b0e41d4f5 | |
| parent | 7df3e93aa953148841bd8a086cb3230f3d01a14c (diff) | |
| download | qemu-eb66e6a96904e50a9d0d1a76aecfe8675f4d8673.zip qemu-eb66e6a96904e50a9d0d1a76aecfe8675f4d8673.tar.gz qemu-eb66e6a96904e50a9d0d1a76aecfe8675f4d8673.tar.bz2 | |
target-s390: Convert CLCLE, MVCLE
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target-s390x/insn-data.def | 4 | ||||
| -rw-r--r-- | target-s390x/translate.c | 50 |
2 files changed, 28 insertions, 26 deletions
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 2e09838..4d7f862 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -132,6 +132,8 @@ C(0xc60e, CLGFRL, RIL_b, GIE, r1_o, mri2_32u, 0, 0, 0, cmpu64) C(0xc607, CLHRL, RIL_b, GIE, r1_o, mri2_16u, 0, 0, 0, cmpu32) C(0xc606, CLGHRL, RIL_b, GIE, r1_o, mri2_16u, 0, 0, 0, cmpu64) +/* COMPARE LOGICAL LONG EXTENDED */ + C(0xa900, CLCLE, RS_a, Z, 0, a2, 0, 0, clcle, 0) /* CONVERT TO DECIMAL */ C(0x4e00, CVD, RX_a, Z, r1_o, a2, 0, 0, cvd, 0) @@ -291,6 +293,8 @@ C(0xeb52, MVIY, SIY, LD, la1, i2, 0, m1_8, mov2, 0) /* MOVE LONG */ C(0x0e00, MVCL, RR_a, Z, 0, 0, 0, 0, mvcl, 0) +/* MOVE LONG EXTENDED */ + C(0xa800, MVCLE, RS_a, Z, 0, a2, 0, 0, mvcle, 0) /* MULTIPLY */ C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index b2a258f..38eeead 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2233,32 +2233,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) LOG_DISAS("opc 0x%x\n", opc); switch (opc) { - case 0xa8: /* MVCLE R1,R3,D2(B2) [RS] */ - insn = ld_code4(env, s->pc); - decode_rs(s, insn, &r1, &r3, &b2, &d2); - tmp = get_address(s, 0, b2, d2); - tmp32_1 = tcg_const_i32(r1); - tmp32_2 = tcg_const_i32(r3); - potential_page_fault(s); - gen_helper_mvcle(cc_op, cpu_env, tmp32_1, tmp, tmp32_2); - set_cc_static(s); - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i32(tmp32_2); - break; - case 0xa9: /* CLCLE R1,R3,D2(B2) [RS] */ - insn = ld_code4(env, s->pc); - decode_rs(s, insn, &r1, &r3, &b2, &d2); - tmp = get_address(s, 0, b2, d2); - tmp32_1 = tcg_const_i32(r1); - tmp32_2 = tcg_const_i32(r3); - potential_page_fault(s); - gen_helper_clcle(cc_op, cpu_env, tmp32_1, tmp, tmp32_2); - set_cc_static(s); - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i32(tmp32_2); - break; #ifndef CONFIG_USER_ONLY case 0xae: /* SIGP R1,R3,D2(B2) [RS] */ check_privileged(s); @@ -3028,6 +3002,18 @@ static ExitStatus op_bct64(DisasContext *s, DisasOps *o) return help_branch(s, &c, is_imm, imm, o->in2); } +static ExitStatus op_clcle(DisasContext *s, DisasOps *o) +{ + TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); + TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); + potential_page_fault(s); + gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3); + tcg_temp_free_i32(r1); + tcg_temp_free_i32(r3); + set_cc_static(s); + return NO_EXIT; +} + static ExitStatus op_cvd(DisasContext *s, DisasOps *o) { TCGv_i64 t1 = tcg_temp_new_i64(); @@ -3348,6 +3334,18 @@ static ExitStatus op_mvcl(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_mvcle(DisasContext *s, DisasOps *o) +{ + TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); + TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3)); + potential_page_fault(s); + gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3); + tcg_temp_free_i32(r1); + tcg_temp_free_i32(r3); + set_cc_static(s); + return NO_EXIT; +} + static ExitStatus op_mul(DisasContext *s, DisasOps *o) { tcg_gen_mul_i64(o->out, o->in1, o->in2); |