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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2022-11-02 16:25:46 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-01-13 09:32:32 +0100 |
| commit | cf386ca8ab20ecad5efa535f3d48750df740da39 (patch) | |
| tree | 912463ada912a50d1b854a996306327025ff5806 | |
| parent | cd5066f8618bc6c80ec9088923c58f4a42ab0e7a (diff) | |
| download | qemu-cf386ca8ab20ecad5efa535f3d48750df740da39.zip qemu-cf386ca8ab20ecad5efa535f3d48750df740da39.tar.gz qemu-cf386ca8ab20ecad5efa535f3d48750df740da39.tar.bz2 | |
hw/mips/bootloader: Implement nanoMIPS NOP opcode generator
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221211204533.85359-3-philmd@linaro.org>
| -rw-r--r-- | hw/mips/bootloader.c | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 21ffd4d..0035f37 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -54,16 +54,32 @@ static bool bootcpu_supports_isa(uint64_t isa_mask) return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask); } -/* Base types */ -static void bl_gen_nop(void **ptr) +static void st_nm32_p(void **ptr, uint32_t insn) { - uint32_t *p = *ptr; + uint16_t *p = *ptr; - stl_p(p, 0); + stw_p(p, insn >> 16); + p++; + stw_p(p, insn >> 0); p++; + *ptr = p; } +/* Base types */ +static void bl_gen_nop(void **ptr) +{ + if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + st_nm32_p(ptr, 0x8000c000); + } else { + uint32_t *p = *ptr; + + stl_p(p, 0); + p++; + *ptr = p; + } +} + static void bl_gen_r_type(void **ptr, uint8_t opcode, bl_reg rs, bl_reg rt, bl_reg rd, uint8_t shift, uint8_t funct) |