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authorMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2021-11-18 18:18:34 +0000
committerMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2021-11-21 09:56:52 +0000
commitc29cd47e82df0bc7385cdd49a158d838314daa9e (patch)
treee17b19d26b3694212bc4babee384ba119053e968
parent8627edfb3f1fca24a96a0954148885c3241c10f8 (diff)
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escc: always set STATUS_TXEMPTY in R_STATUS on device reset
The "Transmit Interrupts and Transmit Buffer Empty Bit" section of the ESCC datasheet states the following about the STATUS_TXEMPTY bit: "After a hardware reset (including a hardware reset by software), or a channel reset, this bit is set to 1". Update escc_reset() to set the STATUS_TXEMPTY bit in the R_STATUS register on device reset as described which fixes a regression whereby the Sun PROM checks this bit early on startup and gets stuck in an infinite loop if it is not set. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20211118181835.18497-2-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/char/escc.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 0fce4f6..a7d9050 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -354,6 +354,17 @@ static void escc_reset(DeviceState *d)
cs->rregs[j] = 0;
cs->wregs[j] = 0;
}
+
+ /*
+ * ...but there is an exception. The "Transmit Interrupts and Transmit
+ * Buffer Empty Bit" section on page 50 of the ESCC datasheet says of
+ * the STATUS_TXEMPTY bit in R_STATUS: "After a hardware reset
+ * (including a hardware reset by software), or a channel reset, this
+ * bit is set to 1". The Sun PROM checks this bit early on startup and
+ * gets stuck in an infinite loop if it is not set.
+ */
+ cs->rregs[R_STATUS] |= STATUS_TXEMPTY;
+
escc_reset_chn(cs);
}
}