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| author | Andreas Färber <afaerber@suse.de> | 2013-01-16 03:48:37 +0100 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-02-16 14:50:57 +0100 |
| commit | c1caf1d961288e41c25de6631c6751ae7baa20f0 (patch) | |
| tree | 282ab0ab9836b6b8abf8bd4db576be18159dc93d | |
| parent | 746b03b27cac48be5a376d8635ffaf568339ebd7 (diff) | |
| download | qemu-c1caf1d961288e41c25de6631c6751ae7baa20f0.zip qemu-c1caf1d961288e41c25de6631c6751ae7baa20f0.tar.gz qemu-c1caf1d961288e41c25de6631c6751ae7baa20f0.tar.bz2 | |
target-mips: Introduce QOM realizefn for MIPSCPU
Introduce a realizefn and set realized = true from cpu_mips_init().
Signed-off-by: Andreas Färber <afaerber@suse.de>
| -rw-r--r-- | target-mips/cpu-qom.h | 2 | ||||
| -rw-r--r-- | target-mips/cpu.c | 15 | ||||
| -rw-r--r-- | target-mips/translate.c | 5 |
3 files changed, 20 insertions, 2 deletions
diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h index 2a4b812..55aa692 100644 --- a/target-mips/cpu-qom.h +++ b/target-mips/cpu-qom.h @@ -37,6 +37,7 @@ /** * MIPSCPUClass: + * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * * A MIPS CPU model. @@ -46,6 +47,7 @@ typedef struct MIPSCPUClass { CPUClass parent_class; /*< public >*/ + DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); } MIPSCPUClass; diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 10ff46d..18895da 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -42,6 +42,17 @@ static void mips_cpu_reset(CPUState *s) cpu_state_reset(env); } +static void mips_cpu_realizefn(DeviceState *dev, Error **errp) +{ + MIPSCPU *cpu = MIPS_CPU(dev); + MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); + + cpu_reset(CPU(cpu)); + qemu_init_vcpu(&cpu->env); + + mcc->parent_realize(dev, errp); +} + static void mips_cpu_initfn(Object *obj) { MIPSCPU *cpu = MIPS_CPU(obj); @@ -54,6 +65,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c); + DeviceClass *dc = DEVICE_CLASS(c); + + mcc->parent_realize = dc->realize; + dc->realize = mips_cpu_realizefn; mcc->parent_reset = cc->reset; cc->reset = mips_cpu_reset; diff --git a/target-mips/translate.c b/target-mips/translate.c index 3b77b53..d7f650e 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15916,8 +15916,9 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) fpu_init(env, def); mvp_init(env, def); mips_tcg_init(); - cpu_reset(CPU(cpu)); - qemu_init_vcpu(env); + + object_property_set_bool(OBJECT(cpu), true, "realized", NULL); + return cpu; } |