diff options
| author | Edgar E. Iglesias <edgar.iglesias@petalogix.com> | 2010-09-09 09:58:35 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2010-09-09 09:58:35 +0200 |
| commit | bdc0bf29c65dbd4f7d5119435e0d05da5de2b5c4 (patch) | |
| tree | 4280927a1040d97eac81d7fa7d22a9d384f68134 | |
| parent | 8b33d9eeba91422ee2d73b6936ad57262d18cf5a (diff) | |
| download | qemu-bdc0bf29c65dbd4f7d5119435e0d05da5de2b5c4.zip qemu-bdc0bf29c65dbd4f7d5119435e0d05da5de2b5c4.tar.gz qemu-bdc0bf29c65dbd4f7d5119435e0d05da5de2b5c4.tar.bz2 | |
microblaze: Add definitions for FSR reg fields
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
| -rw-r--r-- | target-microblaze/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 360ac0a..dfcf25a 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -91,6 +91,13 @@ struct CPUMBState; #define ESR_EC_DATA_TLB 10 #define ESR_EC_INSN_TLB 11 +/* Floating Point Status Register (FSR) Bits */ +#define FSR_IO (1<<4) /* Invalid operation */ +#define FSR_DZ (1<<3) /* Divide-by-zero */ +#define FSR_OF (1<<2) /* Overflow */ +#define FSR_UF (1<<1) /* Underflow */ +#define FSR_DO (1<<0) /* Denormalized operand error */ + /* Version reg. */ /* Basic PVR mask */ #define PVR0_PVR_FULL_MASK 0x80000000 |