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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-23 09:54:20 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-11-02 14:32:32 +0100 |
| commit | bbc213b37c1366cf64701d37a21b709c97714a2d (patch) | |
| tree | d564bf96879997433d05bb20c60e862f9ff642ee | |
| parent | 36b39a69b2e7649d317a08dd81da39a7c9bc14f3 (diff) | |
| download | qemu-bbc213b37c1366cf64701d37a21b709c97714a2d.zip qemu-bbc213b37c1366cf64701d37a21b709c97714a2d.tar.gz qemu-bbc213b37c1366cf64701d37a21b709c97714a2d.tar.bz2 | |
target/mips: Adjust style in msa_translate_init()
While the first 'off' variable assignment is unused, it helps
to better understand the code logic. Move the assignation where
it would have been used so it is easier to compare the MSA
registers based on FPU ones versus the MSA specific registers.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211023214803.522078-34-f4bug@amsat.org>
| -rw-r--r-- | target/mips/tcg/msa_translate.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 3ef912d..3aa15e1 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -280,13 +280,15 @@ void msa_translate_init(void) int i; for (i = 0; i < 32; i++) { - int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + int off; /* * The MSA vector registers are mapped on the * scalar floating-point unit (FPU) registers. */ + off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); msa_wr_d[i * 2] = fpu_f64[i]; + off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] = tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); |