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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-19 08:22:31 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-11-02 14:32:32 +0100 |
| commit | 75094c334e4c2f6d4646274cd73006d8931a31de (patch) | |
| tree | 63a5a5932fd5c81207e4bb24d4d729d5076b1246 | |
| parent | d61566cf78d97952ecf6a00a64b168c61fadd4ce (diff) | |
| download | qemu-75094c334e4c2f6d4646274cd73006d8931a31de.zip qemu-75094c334e4c2f6d4646274cd73006d8931a31de.tar.gz qemu-75094c334e4c2f6d4646274cd73006d8931a31de.tar.bz2 | |
target/mips: Convert MSA LDI opcode to decodetree
Convert the LDI opcode (Immediate Load) to decodetree. Since it
overlaps with the generic MSA handler, use a decodetree overlap
group.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-9-f4bug@amsat.org>
| -rw-r--r-- | target/mips/tcg/msa.decode | 8 | ||||
| -rw-r--r-- | target/mips/tcg/msa_translate.c | 22 |
2 files changed, 21 insertions, 9 deletions
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 56419a2..bdfe5a2 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -14,10 +14,12 @@ &r rs rt rd sa &msa_bz df wt sa +&msa_ldi df wd sa @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa @@ -27,4 +29,8 @@ BNZ_V 010001 01111 ..... ................ @bz_v BZ 010001 110 .. ..... ................ @bz BNZ 010001 111 .. ..... ................ @bz -MSA 011110 -------------------------- +{ + LDI 011110 110 .. .......... ..... 000111 @ldi + + MSA 011110 -------------------------- +} diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 8311730..94c69a6 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -70,7 +70,6 @@ enum { OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07, OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06, OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07, - OPC_LDI_df = (0x6 << 23) | OPC_MSA_I5_07, /* I8 instruction */ OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00, @@ -515,13 +514,6 @@ static void gen_msa_i5(DisasContext *ctx) case OPC_CLEI_U_df: gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); break; - case OPC_LDI_df: - { - int32_t s10 = sextract32(ctx->opcode, 11, 10); - tcg_gen_movi_i32(timm, s10); - gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -534,6 +526,20 @@ static void gen_msa_i5(DisasContext *ctx) tcg_temp_free_i32(timm); } +static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_ldi_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->sa)); + + return true; +} + static void gen_msa_bit(DisasContext *ctx) { #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) |