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authorLucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>2021-11-04 09:37:07 -0300
committerDavid Gibson <david@gibson.dropbear.id.au>2021-11-09 10:32:53 +1100
commit70426b5bb738c3d8b70d6f7484c2a9b91739ac54 (patch)
tree4f80359fbd5db557a8116d858c110d8f6cc1845b
parent72b70d5c3cdca7eaa7be448a1dc91af52167b9ab (diff)
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target/ppc: moved stxvx and lxvx from legacy to decodtree
Moved stxvx and lxvx implementation from the legacy system to decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211104123719.323713-14-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat
-rw-r--r--target/ppc/insn32.decode5
-rw-r--r--target/ppc/translate/vsx-impl.c.inc121
-rw-r--r--target/ppc/translate/vsx-ops.c.inc2
3 files changed, 20 insertions, 108 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 296d6d6..3ce26b2 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -103,6 +103,9 @@
@X_tbp_s_rc ...... ....0 s:1 .... ....0 .......... rc:1 &X_tb_s_rc rt=%x_frtp rb=%x_frbp
+%x_rt_tsx 0:1 21:5
+@X_TSX ...... ..... ra:5 rb:5 .......... . &X rt=%x_rt_tsx
+
&X_frtp_vrb frtp vrb
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
@@ -393,3 +396,5 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
+LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
+STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 9da66b5..1973bb1 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -255,112 +255,6 @@ static void gen_lxvb16x(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
-#define VSX_VECTOR_LOAD(name, op, indexed) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- int xt; \
- TCGv EA; \
- TCGv_i64 xth; \
- TCGv_i64 xtl; \
- \
- if (indexed) { \
- xt = xT(ctx->opcode); \
- } else { \
- xt = DQxT(ctx->opcode); \
- } \
- \
- if (xt < 32) { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- } else { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- } \
- xth = tcg_temp_new_i64(); \
- xtl = tcg_temp_new_i64(); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (indexed) { \
- gen_addr_reg_index(ctx, EA); \
- } else { \
- gen_addr_imm_index(ctx, EA, 0x0F); \
- } \
- if (ctx->le_mode) { \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsr(xt, xtl, false); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsr(xt, xth, true); \
- } else { \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsr(xt, xth, true); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsr(xt, xtl, false); \
- } \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
- tcg_temp_free_i64(xtl); \
-}
-
-VSX_VECTOR_LOAD(lxvx, ld_i64, 1)
-
-#define VSX_VECTOR_STORE(name, op, indexed) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- int xt; \
- TCGv EA; \
- TCGv_i64 xth; \
- TCGv_i64 xtl; \
- \
- if (indexed) { \
- xt = xT(ctx->opcode); \
- } else { \
- xt = DQxT(ctx->opcode); \
- } \
- \
- if (xt < 32) { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- } else { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- } \
- xth = tcg_temp_new_i64(); \
- xtl = tcg_temp_new_i64(); \
- get_cpu_vsr(xth, xt, true); \
- get_cpu_vsr(xtl, xt, false); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (indexed) { \
- gen_addr_reg_index(ctx, EA); \
- } else { \
- gen_addr_imm_index(ctx, EA, 0x0F); \
- } \
- if (ctx->le_mode) { \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
- } else { \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
- } \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
- tcg_temp_free_i64(xtl); \
-}
-
-VSX_VECTOR_STORE(stxvx, st_i64, 1)
-
#ifdef TARGET_PPC64
#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
static void gen_##name(DisasContext *ctx) \
@@ -2096,8 +1990,23 @@ static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store)
return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store);
}
+static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+
+ if (a->rt >= 32) {
+ REQUIRE_VSX(ctx);
+ } else {
+ REQUIRE_VECTOR(ctx);
+ }
+
+ return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store);
+}
+
TRANS(STXV, do_lstxv_D, true)
TRANS(LXV, do_lstxv_D, false)
+TRANS(STXVX, do_lstxv_X, true)
+TRANS(LXVX, do_lstxv_X, false)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 1d41bee..b94f3fa 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -10,7 +10,6 @@ GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvll, 0x1F, 0x0D, 0x09, 0, PPC_NONE, PPC2_ISA300),
@@ -25,7 +24,6 @@ GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300),
generated by cgit v1.1 at 2024-12-26 13:13:52 +0000