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| author | Bin Meng <bin.meng@windriver.com> | 2020-06-08 07:17:37 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-19 08:25:27 -0700 |
| commit | 621c1006d2d82da9f266f21ad8e887c38769a11b (patch) | |
| tree | aa8f0f30f8d1082f9f2a1255568850ead7f49285 | |
| parent | 8a88b9f54f5fb2acecf73760903b1f58fb40d0cd (diff) | |
| download | qemu-621c1006d2d82da9f266f21ad8e887c38769a11b.zip qemu-621c1006d2d82da9f266f21ad8e887c38769a11b.tar.gz qemu-621c1006d2d82da9f266f21ad8e887c38769a11b.tar.bz2 | |
hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | hw/riscv/sifive_gpio.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c index 0d0fd2b..aac6b44 100644 --- a/hw/riscv/sifive_gpio.c +++ b/hw/riscv/sifive_gpio.c @@ -76,7 +76,9 @@ static void update_state(SIFIVEGPIOState *s) actual_value = pull; } - qemu_set_irq(s->output[i], actual_value); + if (output_en) { + qemu_set_irq(s->output[i], actual_value); + } /* Input value */ ival = input_en && actual_value; |