diff options
| author | Stefan Markovic <smarkovic@wavecomp.com> | 2018-10-16 12:17:44 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-18 20:37:20 +0200 |
| commit | 6208f09441dcf8d142ff0e1624ef12da298776a4 (patch) | |
| tree | fbd77f87e64ef5cedb43fab1792ece024ab24aeb | |
| parent | 45ebdd24c3de158890ce390df39855a891e80701 (diff) | |
| download | qemu-6208f09441dcf8d142ff0e1624ef12da298776a4.zip qemu-6208f09441dcf8d142ff0e1624ef12da298776a4.tar.gz qemu-6208f09441dcf8d142ff0e1624ef12da298776a4.tar.bz2 | |
target/mips: Add bit definitions for DSP R3 ASE
Add DSP R3 ASE related bit definition for insn_flags and hflags.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| -rw-r--r-- | target/mips/cpu.h | 1 | ||||
| -rw-r--r-- | target/mips/mips-defs.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3b3509c..7f4e6d0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -795,6 +795,7 @@ struct CPUMIPSState { /* MIPS DSP resources access. */ #define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */ #define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */ +#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resources.*/ /* Extra flag about HWREna register. */ #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 66b7953..a23c4ed 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -53,6 +53,7 @@ #define ASE_MDMX 0x0000000400000000ULL #define ASE_DSP 0x0000000800000000ULL #define ASE_DSPR2 0x0000001000000000ULL +#define ASE_DSPR3 0x0000002000000000ULL #define ASE_MT 0x0000004000000000ULL #define ASE_SMARTMIPS 0x0000008000000000ULL #define ASE_MICROMIPS 0x0000010000000000ULL |