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| author | Paolo Bonzini <pbonzini@redhat.com> | 2014-11-11 13:14:05 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2014-11-24 14:37:30 +0100 |
| commit | 60e68042cf70f271308dc6b4b22b609d054af929 (patch) | |
| tree | eed82dc3faa251f48d8295d025883ad6d3e2c256 | |
| parent | 0e88f478508b566152c6681f4889ed9830a2c0a5 (diff) | |
| download | qemu-60e68042cf70f271308dc6b4b22b609d054af929.zip qemu-60e68042cf70f271308dc6b4b22b609d054af929.tar.gz qemu-60e68042cf70f271308dc6b4b22b609d054af929.tar.bz2 | |
apic: avoid getting out of halted state on masked PIC interrupts
After the next patch, if a masked PIC interrupts causes CPU_INTERRUPT_POLL
to be set, the CPU will spuriously get out of halted state. While this
is technically valid, we should avoid that.
Make CPU_INTERRUPT_POLL run apic_update_irq in the right thread and then
look at CPU_INTERRUPT_HARD. If CPU_INTERRUPT_HARD does not get set,
do not report the CPU as having work.
Also move the handling of software-disabled APIC from apic_update_irq
to apic_irq_pending, and always trigger CPU_INTERRUPT_POLL. This will
be important once we will add a case that resets CPU_INTERRUPT_HARD
from apic_update_irq. We want to run it even if we go through
CPU_INTERRUPT_POLL, and even if the local APIC is software disabled.
Reported-by: Richard Bilson <rbilson@qnx.com>
Tested-by: Richard Bilson <rbilson@qnx.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | hw/intc/apic.c | 8 | ||||
| -rw-r--r-- | target-i386/cpu.c | 10 |
2 files changed, 13 insertions, 5 deletions
diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 03ff9e9..0653409 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -349,6 +349,11 @@ static int apic_get_arb_pri(APICCommonState *s) static int apic_irq_pending(APICCommonState *s) { int irrv, ppr; + + if (!(s->spurious_vec & APIC_SV_ENABLE)) { + return 0; + } + irrv = get_highest_priority_int(s->irr); if (irrv < 0) { return 0; @@ -366,9 +371,6 @@ static void apic_update_irq(APICCommonState *s) { CPUState *cpu; - if (!(s->spurious_vec & APIC_SV_ENABLE)) { - return; - } cpu = CPU(s->cpu); if (!qemu_cpu_is_self(cpu)) { cpu_interrupt(cpu, CPU_INTERRUPT_POLL); diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 3f13dfe..e9df33e 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2912,8 +2912,14 @@ static bool x86_cpu_has_work(CPUState *cs) X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; - return ((cs->interrupt_request & (CPU_INTERRUPT_HARD | - CPU_INTERRUPT_POLL)) && +#if !defined(CONFIG_USER_ONLY) + if (cs->interrupt_request & CPU_INTERRUPT_POLL) { + apic_poll_irq(cpu->apic_state); + cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL); + } +#endif + + return ((cs->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || (cs->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_INIT | |