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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-06 13:02:22 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-09 11:47:53 +0100 |
| commit | 52d187275b3a306c6bc83c083885ae34e0939f0d (patch) | |
| tree | ac09e3ae45bca60e3f9e6a5d0096ddc87904afd8 | |
| parent | 60360d82a1022f8db9cbe5ed312de14b490fa46e (diff) | |
| download | qemu-52d187275b3a306c6bc83c083885ae34e0939f0d.zip qemu-52d187275b3a306c6bc83c083885ae34e0939f0d.tar.gz qemu-52d187275b3a306c6bc83c083885ae34e0939f0d.tar.bz2 | |
target/arm: Adjust definition of CONTEXTIDR_EL2
This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 72d0507..7b31c71 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7246,11 +7246,14 @@ static const ARMCPRegInfo jazelle_regs[] = { .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, }; +static const ARMCPRegInfo contextidr_el2 = { + .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, + .access = PL2_RW, + .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) +}; + static const ARMCPRegInfo vhe_reginfo[] = { - { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, - .access = PL2_RW, - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, @@ -8215,6 +8218,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &ssbs_reginfo); } + if (cpu_isar_feature(aa64_vh, cpu) || + cpu_isar_feature(aa64_debugv8p2, cpu)) { + define_one_arm_cp_reg(cpu, &contextidr_el2); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { define_arm_cp_regs(cpu, vhe_reginfo); } |