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author | Edgar E. Iglesias <edgar.iglesias@petalogix.com> | 2010-07-24 23:25:49 +0200 |
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committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2010-07-24 23:25:49 +0200 |
commit | 4b5ef0b50da39a9672524a39484512fe3ab56eb5 (patch) | |
tree | 1e60d76c06a41dca34a5cc5e43d7bbef925d7554 | |
parent | b2565c694a1e9377a57594aa74f1778f7aa9a5e8 (diff) | |
download | qemu-4b5ef0b50da39a9672524a39484512fe3ab56eb5.zip qemu-4b5ef0b50da39a9672524a39484512fe3ab56eb5.tar.gz qemu-4b5ef0b50da39a9672524a39484512fe3ab56eb5.tar.bz2 |
microblaze: Speed up base + index addressing mode
Speed up reg + reg addressing mode when any of the regs is r0.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
-rw-r--r-- | target-microblaze/translate.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 3a766d8..9c0492e 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -788,6 +788,13 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) /* Treat the fast cases first. */ if (!dc->type_b) { + /* If any of the regs is r0, return a ptr to the other. */ + if (dc->ra == 0) { + return &cpu_R[dc->rb]; + } else if (dc->rb == 0) { + return &cpu_R[dc->ra]; + } + *t = tcg_temp_new(); tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]); return t; |