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authorVitaly Kuznetsov <vkuznets@redhat.com>2022-05-25 13:59:48 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2022-05-25 21:26:35 +0200
commit3aae0854b26aff303202c6f9542445f58b2539fe (patch)
tree3ed994c14b2231190f4e3b70ce09d78260276766
parentaa6bb5fad58d049c6ea97448d4caba4499d60634 (diff)
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i386: Hyper-V Direct TLB flush hypercall
Hyper-V TLFS allows for L0 and L1 hypervisors to collaborate on L2's TLB flush hypercalls handling. With the correct setup, L2's TLB flush hypercalls can be handled by L0 directly, without the need to exit to L1. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20220525115949.1294004-6-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
-rw-r--r--docs/hyperv.txt11
-rw-r--r--target/i386/cpu.c2
-rw-r--r--target/i386/cpu.h1
-rw-r--r--target/i386/kvm/hyperv-proto.h1
-rw-r--r--target/i386/kvm/kvm.c8
5 files changed, 23 insertions, 0 deletions
diff --git a/docs/hyperv.txt b/docs/hyperv.txt
index 4b132b1..14a7f44 100644
--- a/docs/hyperv.txt
+++ b/docs/hyperv.txt
@@ -262,6 +262,17 @@ Allow for extended GVA ranges to be passed to Hyper-V TLB flush hypercalls
Requires: hv-tlbflush
+3.25. hv-tlbflush-direct
+=========================
+The enlightenment is nested specific, it targets Hyper-V on KVM guests. When
+enabled, it allows L0 (KVM) to directly handle TLB flush hypercalls from L2
+guest without the need to exit to L1 (Hyper-V) hypervisor. While the feature is
+supported for both VMX (Intel) and SVM (AMD), the VMX implementation requires
+Enlightened VMCS ('hv-evmcs') feature to also be enabled.
+
+Requires: hv-vapic
+Recommended: hv-evmcs (Intel)
+
4. Supplementary features
=========================
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3429a4e..bb6a5dd 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6974,6 +6974,8 @@ static Property x86_cpu_properties[] = {
HYPERV_FEAT_XMM_INPUT, 0),
DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features,
HYPERV_FEAT_TLBFLUSH_EXT, 0),
+ DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features,
+ HYPERV_FEAT_TLBFLUSH_DIRECT, 0),
DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 5ff4825..82004b6 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1109,6 +1109,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
#define HYPERV_FEAT_MSR_BITMAP 17
#define HYPERV_FEAT_XMM_INPUT 18
#define HYPERV_FEAT_TLBFLUSH_EXT 19
+#define HYPERV_FEAT_TLBFLUSH_DIRECT 20
#ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
#define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
diff --git a/target/i386/kvm/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h
index c7854ed..464fbf0 100644
--- a/target/i386/kvm/hyperv-proto.h
+++ b/target/i386/kvm/hyperv-proto.h
@@ -90,6 +90,7 @@
/*
* HV_CPUID_NESTED_FEATURES.EAX bits
*/
+#define HV_NESTED_DIRECT_FLUSH (1u << 17)
#define HV_NESTED_MSR_BITMAP (1u << 19)
/*
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index a11c8e8..f148a6d 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -995,6 +995,14 @@ static struct {
},
.dependencies = BIT(HYPERV_FEAT_TLBFLUSH)
},
+ [HYPERV_FEAT_TLBFLUSH_DIRECT] = {
+ .desc = "direct TLB flush (hv-tlbflush-direct)",
+ .flags = {
+ {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
+ .bits = HV_NESTED_DIRECT_FLUSH}
+ },
+ .dependencies = BIT(HYPERV_FEAT_VAPIC)
+ },
};
static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,