diff options
| author | Cédric Le Goater <clg@kaod.org> | 2021-01-26 18:10:53 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-02-10 10:43:50 +1100 |
| commit | 2cfc9f1a968f8f832c7bf23f2491b058bdde028b (patch) | |
| tree | 1e4ad06f7232b237ba0c12238dff8f21407b9439 | |
| parent | 1f38f48900f6ebfa80f958bda8e2ec81ad4dabb9 (diff) | |
| download | qemu-2cfc9f1a968f8f832c7bf23f2491b058bdde028b.zip qemu-2cfc9f1a968f8f832c7bf23f2491b058bdde028b.tar.gz qemu-2cfc9f1a968f8f832c7bf23f2491b058bdde028b.tar.bz2 | |
ppc/pnv: Add trace events for PCI event notification
On POWER9 systems, PHB controllers signal the XIVE interrupt controller
of a source interrupt notification using a store on a MMIO region. Add
traces for such events.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210126171059.307867-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| -rw-r--r-- | hw/intc/pnv_xive.c | 3 | ||||
| -rw-r--r-- | hw/intc/trace-events | 3 | ||||
| -rw-r--r-- | hw/pci-host/pnv_phb4.c | 3 | ||||
| -rw-r--r-- | hw/pci-host/trace-events | 3 |
4 files changed, 12 insertions, 0 deletions
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 5f69626..ad43483 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -24,6 +24,7 @@ #include "hw/ppc/xive_regs.h" #include "hw/qdev-properties.h" #include "hw/ppc/ppc.h" +#include "trace.h" #include <libfdt.h> @@ -1319,6 +1320,8 @@ static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr addr, uint64_t val) uint8_t blk; uint32_t idx; + trace_pnv_xive_ic_hw_trigger(addr, val); + if (val & XIVE_TRIGGER_END) { xive_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, addr, val); diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 8ed397a..45ddaf4 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -236,3 +236,6 @@ xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x0x%"P xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x0x%"PRIx64" sz=%d val=0x%" PRIx64 xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "found NVT 0x%x/0x%x ring=0x%x" xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END 0x%x/0x%x @0x0x%"PRIx64 + +# pnv_xive.c +pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64" val=0x%"PRIx64 diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 6328e98..54f57c6 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -22,6 +22,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "qom/object.h" +#include "trace.h" #define phb_error(phb, fmt, ...) \ qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \ @@ -1257,6 +1258,8 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno) uint64_t data = XIVE_TRIGGER_PQ | offset | srcno; MemTxResult result; + trace_pnv_phb4_xive_notify(notif_port, data); + address_space_stq_be(&address_space_memory, notif_port, data, MEMTXATTRS_UNSPECIFIED, &result); if (result != MEMTX_OK) { diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index d19ca9a..7d8063a 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -20,3 +20,6 @@ unin_data_write(uint64_t addr, unsigned len, uint64_t val) "write addr 0x%"PRIx6 unin_data_read(uint64_t addr, unsigned len, uint64_t val) "read addr 0x%"PRIx64 " len %d val 0x%"PRIx64 unin_write(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64 unin_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64 + +# pnv_phb4.c +pnv_phb4_xive_notify(uint64_t notif_port, uint64_t data) "notif=@0x%"PRIx64" data=0x%"PRIx64 |