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authorIris Chen <irischenlj@fb.com>2022-06-30 09:21:13 +0200
committerCédric Le Goater <clg@kaod.org>2022-06-30 09:21:13 +0200
commit1de51272bf7f71ccf4b1503f5b1018ca6d429675 (patch)
treea068303c818cdaa31407f2cc5e0688e56730bcc4
parent2fa22a0f60f98739c4b3534d91826b68a51195ad (diff)
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hw: m25p80: add tests for write protect (WP# and SRWD bit)
Signed-off-by: Iris Chen <irischenlj@fb.com> Message-Id: <20220624183016.2125264-1-irischenlj@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
-rw-r--r--tests/qtest/aspeed_smc-test.c62
1 files changed, 62 insertions, 0 deletions
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index b1e682d..1258687 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -56,7 +56,9 @@ enum {
BULK_ERASE = 0xc7,
READ = 0x03,
PP = 0x02,
+ WRSR = 0x1,
WREN = 0x6,
+ SRWD = 0x80,
RESET_ENABLE = 0x66,
RESET_MEMORY = 0x99,
EN_4BYTE_ADDR = 0xB7,
@@ -441,6 +443,64 @@ static void test_read_status_reg(void)
flash_reset();
}
+static void test_status_reg_write_protection(void)
+{
+ uint8_t r;
+
+ spi_conf(CONF_ENABLE_W0);
+
+ /* default case: WP# is high and SRWD is low -> status register writable */
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, WREN);
+ /* test ability to write SRWD */
+ writeb(ASPEED_FLASH_BASE, WRSR);
+ writeb(ASPEED_FLASH_BASE, SRWD);
+ writeb(ASPEED_FLASH_BASE, RDSR);
+ r = readb(ASPEED_FLASH_BASE);
+ spi_ctrl_stop_user();
+ g_assert_cmphex(r & SRWD, ==, SRWD);
+
+ /* WP# high and SRWD high -> status register writable */
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, WREN);
+ /* test ability to write SRWD */
+ writeb(ASPEED_FLASH_BASE, WRSR);
+ writeb(ASPEED_FLASH_BASE, 0);
+ writeb(ASPEED_FLASH_BASE, RDSR);
+ r = readb(ASPEED_FLASH_BASE);
+ spi_ctrl_stop_user();
+ g_assert_cmphex(r & SRWD, ==, 0);
+
+ /* WP# low and SRWD low -> status register writable */
+ qtest_set_irq_in(global_qtest,
+ "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, WREN);
+ /* test ability to write SRWD */
+ writeb(ASPEED_FLASH_BASE, WRSR);
+ writeb(ASPEED_FLASH_BASE, SRWD);
+ writeb(ASPEED_FLASH_BASE, RDSR);
+ r = readb(ASPEED_FLASH_BASE);
+ spi_ctrl_stop_user();
+ g_assert_cmphex(r & SRWD, ==, SRWD);
+
+ /* WP# low and SRWD high -> status register NOT writable */
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, WREN);
+ /* test ability to write SRWD */
+ writeb(ASPEED_FLASH_BASE, WRSR);
+ writeb(ASPEED_FLASH_BASE, 0);
+ writeb(ASPEED_FLASH_BASE, RDSR);
+ r = readb(ASPEED_FLASH_BASE);
+ spi_ctrl_stop_user();
+ /* write is not successful */
+ g_assert_cmphex(r & SRWD, ==, SRWD);
+
+ qtest_set_irq_in(global_qtest,
+ "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
+ flash_reset();
+}
+
static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX";
int main(int argc, char **argv)
@@ -467,6 +527,8 @@ int main(int argc, char **argv)
qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem);
qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem);
qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg);
+ qtest_add_func("/ast2400/smc/status_reg_write_protection",
+ test_status_reg_write_protection);
flash_reset();
ret = g_test_run();