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| author | Paolo Bonzini <pbonzini@redhat.com> | 2015-11-06 16:34:06 +0100 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2015-12-04 09:39:55 +0300 |
| commit | 63fc7375d6b0a083aef56950119af3d1d2a96e51 (patch) | |
| tree | 8cdfeac2cc8a5764bc48ddb69288526eacdcdbdd | |
| parent | fccd35a04640a728f979e6d72b2c7d02c05549f0 (diff) | |
| download | qemu-63fc7375d6b0a083aef56950119af3d1d2a96e51.zip qemu-63fc7375d6b0a083aef56950119af3d1d2a96e51.tar.gz qemu-63fc7375d6b0a083aef56950119af3d1d2a96e51.tar.bz2 | |
gt64xxx: fix decoding of ISD register
The GT64xxx's internal registers can be placed above the first 4 GiB
in the address space, but not above the first 64 GiB. Correctly cast
the register to a 64-bit integer, and mask away bits above bit 35.
Datasheet at http://pdf.datasheetarchive.com/datasheetsmain/Datasheets-33/DSA-655889.pdf
(bug reported by Coverity).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| -rw-r--r-- | hw/mips/gt64xxx_pci.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 10fcca3..f76a9fd 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -275,7 +275,8 @@ static void check_reserved_space (hwaddr *start, static void gt64120_isd_mapping(GT64120State *s) { - hwaddr start = s->regs[GT_ISD] << 21; + /* Bits 14:0 of ISD map to bits 35:21 of the start address. */ + hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull; hwaddr length = 0x1000; if (s->ISD_length) { |