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authorAlexander Graf <agraf@suse.de>2010-12-08 12:05:38 +0100
committerBlue Swirl <blauwirbel@gmail.com>2010-12-11 15:24:25 +0000
commit6bef04365589b1b82be1a1c3aa223f4bddb3dabb (patch)
tree73c3d79035f5196037236cd2117bdc8dcb8ed6ad
parent2507c12ab026b2286b0a47035c629f3d568c96f4 (diff)
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Make simple io mem handler endian aware
As an alternative to the 3 individual handlers, there is also a simplified io mem hook function. To be consistent, let's add an endianness parameter there too. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
-rw-r--r--hw/apb_pci.c3
-rw-r--r--hw/pci_host.c12
-rw-r--r--hw/unin_pci.c6
-rw-r--r--rwhandler.c4
-rw-r--r--rwhandler.h2
5 files changed, 17 insertions, 10 deletions
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index bf00c71..84e9af7 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -418,7 +418,8 @@ static int pci_pbm_init_device(SysBusDevice *dev)
/* PCI configuration space */
s->pci_config_handler.read = apb_pci_config_read;
s->pci_config_handler.write = apb_pci_config_write;
- pci_config = cpu_register_io_memory_simple(&s->pci_config_handler);
+ pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
+ DEVICE_NATIVE_ENDIAN);
assert(pci_config >= 0);
/* at region 1 */
sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
diff --git a/hw/pci_host.c b/hw/pci_host.c
index bc5b771..a6e39c9 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -187,9 +187,11 @@ int pci_host_conf_register_mmio(PCIHostState *s, int swap)
{
pci_host_init(s);
if (swap) {
- return cpu_register_io_memory_simple(&s->conf_handler);
+ return cpu_register_io_memory_simple(&s->conf_handler,
+ DEVICE_NATIVE_ENDIAN);
} else {
- return cpu_register_io_memory_simple(&s->conf_noswap_handler);
+ return cpu_register_io_memory_simple(&s->conf_noswap_handler,
+ DEVICE_NATIVE_ENDIAN);
}
}
@@ -203,9 +205,11 @@ int pci_host_data_register_mmio(PCIHostState *s, int swap)
{
pci_host_init(s);
if (swap) {
- return cpu_register_io_memory_simple(&s->data_handler);
+ return cpu_register_io_memory_simple(&s->data_handler,
+ DEVICE_NATIVE_ENDIAN);
} else {
- return cpu_register_io_memory_simple(&s->data_noswap_handler);
+ return cpu_register_io_memory_simple(&s->data_noswap_handler,
+ DEVICE_NATIVE_ENDIAN);
}
}
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 1310211..53791dd 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -154,7 +154,8 @@ static int pci_unin_main_init_device(SysBusDevice *dev)
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
- pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
+ pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
@@ -175,7 +176,8 @@ static int pci_u3_agp_init_device(SysBusDevice *dev)
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
- pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
+ pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
diff --git a/rwhandler.c b/rwhandler.c
index 88dfcc5..bb2238f 100644
--- a/rwhandler.c
+++ b/rwhandler.c
@@ -35,14 +35,14 @@ static CPUReadMemoryFunc * const cpu_io_memory_simple_read[] = {
&cpu_io_memory_simple_readl,
};
-int cpu_register_io_memory_simple(struct ReadWriteHandler *handler)
+int cpu_register_io_memory_simple(struct ReadWriteHandler *handler, int endian)
{
if (!handler->read || !handler->write) {
return -1;
}
return cpu_register_io_memory(cpu_io_memory_simple_read,
cpu_io_memory_simple_write,
- handler, DEVICE_NATIVE_ENDIAN);
+ handler, endian);
}
RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t);
diff --git a/rwhandler.h b/rwhandler.h
index bc11849..b2a5790 100644
--- a/rwhandler.h
+++ b/rwhandler.h
@@ -19,7 +19,7 @@ struct ReadWriteHandler {
/* Helpers for when we want to use a single routine with length. */
/* CPU memory handler: both read and write must be present. */
-int cpu_register_io_memory_simple(ReadWriteHandler *);
+int cpu_register_io_memory_simple(ReadWriteHandler *, int endian);
/* io port handler: can supply only read or write handlers. */
int register_ioport_simple(ReadWriteHandler *,
pio_addr_t start, int length, int size);