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| author | Zhao Liu <zhao1.liu@intel.com> | 2025-06-05 21:27:22 +0800 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-06-10 12:59:09 +0200 |
| commit | 59a4757bb4d01c9dfb50e872a9d04ad1f1c38049 (patch) | |
| tree | baafd6ac37aedf400f54db6a3fc305ba2c2ff7c0 | |
| parent | 6cfe590c6b7876ba2471a4357274b33072d62214 (diff) | |
| download | qemu-59a4757bb4d01c9dfb50e872a9d04ad1f1c38049.zip qemu-59a4757bb4d01c9dfb50e872a9d04ad1f1c38049.tar.gz qemu-59a4757bb4d01c9dfb50e872a9d04ad1f1c38049.tar.bz2 | |
hw/core/cpu: Move CacheType to general cpu.h
I386 has already defined cache types in target/i386/cpu.h.
Move CacheType to hw/core/cpu.h, so that ARM and other architectures
could use it.
Cc: Alireza Sanaee <alireza.sanaee@huawei.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250605132722.3597593-1-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| -rw-r--r-- | include/hw/core/cpu.h | 6 | ||||
| -rw-r--r-- | target/i386/cpu.h | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1e87f7d..33296a1 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1126,4 +1126,10 @@ extern const VMStateDescription vmstate_cpu_common; #define UNASSIGNED_CPU_INDEX -1 #define UNASSIGNED_CLUSTER_INDEX -1 +enum CacheType { + DATA_CACHE, + INSTRUCTION_CACHE, + UNIFIED_CACHE +}; + #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 545851c..5910dcf 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1773,12 +1773,6 @@ typedef enum TPRAccess { /* Cache information data structures: */ -enum CacheType { - DATA_CACHE, - INSTRUCTION_CACHE, - UNIFIED_CACHE -}; - typedef struct CPUCacheInfo { enum CacheType type; uint8_t level; |