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| author | Zhao Liu <zhao1.liu@intel.com> | 2025-06-27 11:51:27 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-07-14 10:27:07 +0200 |
| commit | 1c52c470baba1a2cc2d96e14c9f845ec3d2ea8c4 (patch) | |
| tree | 76a41589551a689c82a0119bd820ea7617236b51 | |
| parent | a539cd26145c726fddd19eb0e2c20332960b0245 (diff) | |
| download | qemu-1c52c470baba1a2cc2d96e14c9f845ec3d2ea8c4.zip qemu-1c52c470baba1a2cc2d96e14c9f845ec3d2ea8c4.tar.gz qemu-1c52c470baba1a2cc2d96e14c9f845ec3d2ea8c4.tar.bz2 | |
i386/cpu: Mark CPUID 0x80000007[EBX] as reserved for Intel
Per SDM,
80000007H EAX Reserved = 0.
EBX Reserved = 0.
ECX Reserved = 0.
EDX Bits 07-00: Reserved = 0.
Bit 08: Invariant TSC available if 1.
Bits 31-09: Reserved = 0.
EAX/EBX/ECX in CPUID 0x80000007 leaf are reserved for Intel.
At present, EAX is reserved for AMD, too. And AMD hasn't used ECX in
QEMU. So these 2 registers are both left as 0.
Therefore, only fix the EBX and excode it as 0 for Intel.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Tao Su <tao1.su@linux.intel.com>
Link: https://lore.kernel.org/r/20250627035129.2755537-3-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ae508fa..533c9d9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8376,7 +8376,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } case 0x80000007: *eax = 0; - *ebx = env->features[FEAT_8000_0007_EBX]; + if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) { + *ebx = 0; + } else { + *ebx = env->features[FEAT_8000_0007_EBX]; + } *ecx = 0; *edx = env->features[FEAT_8000_0007_EDX]; break; |