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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-05-24 18:02:48 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-05-25 16:01:43 +0100 |
| commit | fc12b46a461bf6d3632e7c86587e17c379bc5082 (patch) | |
| tree | 10117a446208fef6acd91a379ca65920bc47ff8c | |
| parent | a7e3a90e7322c70586e8d8478cf27e8a91a0ca74 (diff) | |
| download | qemu-fc12b46a461bf6d3632e7c86587e17c379bc5082.zip qemu-fc12b46a461bf6d3632e7c86587e17c379bc5082.tar.gz qemu-fc12b46a461bf6d3632e7c86587e17c379bc5082.tar.bz2 | |
target/arm: Implement SVE2 bitwise shift and insert
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/sve.decode | 5 | ||||
| -rw-r--r-- | target/arm/translate-sve.c | 10 |
2 files changed, 15 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index d3c4ec6..695a165 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1261,3 +1261,8 @@ SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr + +## SVE2 bitwise shift and insert + +SRI 01000101 .. 0 ..... 11110 0 ..... ..... @rd_rn_tszimm_shr +SLI 01000101 .. 0 ..... 11110 1 ..... ..... @rd_rn_tszimm_shl diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 1f93b1e..5e42ba3 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -6428,3 +6428,13 @@ static bool trans_URSRA(DisasContext *s, arg_rri_esz *a) { return do_sve2_fn2i(s, a, gen_gvec_ursra); } + +static bool trans_SRI(DisasContext *s, arg_rri_esz *a) +{ + return do_sve2_fn2i(s, a, gen_gvec_sri); +} + +static bool trans_SLI(DisasContext *s, arg_rri_esz *a) +{ + return do_sve2_fn2i(s, a, gen_gvec_sli); +} |