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| author | Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> | 2020-02-23 15:28:06 +0500 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-03-16 17:03:51 -0700 |
| commit | c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264 (patch) | |
| tree | 081053039d7613158c1214c406369afe4a336c35 | |
| parent | c6fc0fc1a71a0cb09b472cf36dded3c52bd77880 (diff) | |
| download | qemu-c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264.zip qemu-c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264.tar.gz qemu-c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264.tar.bz2 | |
target/riscv: Fix VS mode interrupts forwarding.
Currently riscv_cpu_local_irq_pending is used to find out pending
interrupt and VS mode interrupts are being shifted to represent
S mode interrupts in this function. So when the cause returned by
this function is passed to riscv_cpu_do_interrupt to actually
forward the interrupt, the VS mode forwarding check does not work
as intended and interrupt is actually forwarded to hypervisor. This
patch fixes this issue.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
| -rw-r--r-- | target/riscv/cpu_helper.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5ea5d13..d3ba9ef 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) target_ulong pending = env->mip & env->mie & ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); target_ulong vspending = (env->mip & env->mie & - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); @@ -907,6 +907,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* + * See if we need to adjust cause. Yes if its VS mode interrupt + * no if hypervisor has delegated one of hs mode's interrupt + */ + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || + cause == IRQ_VS_EXT) + cause = cause - 1; /* Trap to VS mode */ } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ |