diff options
| author | Fea.Wang <fea.wang@sifive.com> | 2024-06-06 21:54:53 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-06-26 22:57:49 +1000 |
| commit | 8392a7c148a9d55cae97393f6a5eab3a6edbafd9 (patch) | |
| tree | bb660611a7d73b99346f6ecd2ecabbafc975cd45 | |
| parent | 27796989ac55983e95bc0538310fd5ee2eefba59 (diff) | |
| download | qemu-8392a7c148a9d55cae97393f6a5eab3a6edbafd9.zip qemu-8392a7c148a9d55cae97393f6a5eab3a6edbafd9.tar.gz qemu-8392a7c148a9d55cae97393f6a5eab3a6edbafd9.tar.bz2 | |
target/riscv: Reserve exception codes for sw-check and hw-err
Based on the priv-1.13.0, add the exception codes for Software-check and
Hardware-error.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240606135454.119186-6-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu_bits.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 096a51b..c257c5e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -673,6 +673,8 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */ + RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, |