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| author | Felipe Balbi <balbi@kernel.org> | 2022-12-30 16:57:32 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-01-12 16:50:18 +0000 |
| commit | 829da0dbe3112a78ab3e298222cd42e000e39c70 (patch) | |
| tree | 31e6ec723ac79cd544372955e09020244795da84 | |
| parent | 3db29dcac23da85486704ef9e7a8e7217f7829cd (diff) | |
| download | qemu-829da0dbe3112a78ab3e298222cd42e000e39c70.zip qemu-829da0dbe3112a78ab3e298222cd42e000e39c70.tar.gz qemu-829da0dbe3112a78ab3e298222cd42e000e39c70.tar.bz2 | |
hw/arm/stm32f405: correctly describe the memory layout
STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled
Memory) at a different base address. Correctly describe the memory
layout to give existing FW images a chance to run unmodified.
Reviewed-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Message-id: 20221230145733.200496-2-balbi@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/arm/stm32f405_soc.c | 8 | ||||
| -rw-r--r-- | include/hw/arm/stm32f405_soc.h | 5 |
2 files changed, 12 insertions, 1 deletions
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index c07947d..cef23d7 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -139,6 +139,14 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) } memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); + memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE, + &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm); + armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index 5bb0c8d..249ab54 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -46,7 +46,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) #define FLASH_BASE_ADDRESS 0x08000000 #define FLASH_SIZE (1024 * 1024) #define SRAM_BASE_ADDRESS 0x20000000 -#define SRAM_SIZE (192 * 1024) +#define SRAM_SIZE (128 * 1024) +#define CCM_BASE_ADDRESS 0x10000000 +#define CCM_SIZE (64 * 1024) struct STM32F405State { /*< private >*/ @@ -65,6 +67,7 @@ struct STM32F405State { STM32F2XXADCState adc[STM_NUM_ADCS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; + MemoryRegion ccm; MemoryRegion sram; MemoryRegion flash; MemoryRegion flash_alias; |