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author | Rebecca Cran <rebecca@nuviainc.com> | 2021-05-12 12:23:37 -0600 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2021-05-25 16:01:43 +0100 |
commit | 7b9171cc83f37d078ae7d544d2bacd6a851453d8 (patch) | |
tree | b5fd0b66a46d39a9147f45ef859e2fb22d6ae035 | |
parent | 7113d618505b1ba7a0b029df2d2617a0d0259e37 (diff) | |
download | qemu-7b9171cc83f37d078ae7d544d2bacd6a851453d8.zip qemu-7b9171cc83f37d078ae7d544d2bacd6a851453d8.tar.gz qemu-7b9171cc83f37d078ae7d544d2bacd6a851453d8.tar.bz2 |
target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210512182337.18563-4-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | target/arm/cpu64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0a9e96..f42803e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -651,6 +651,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); cpu->isar.id_aa64isar0 = t; |