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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-04-24 13:28:33 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:07 +1000 |
| commit | 3820602f8059dfd4034d38bb727cdbc8759631db (patch) | |
| tree | 5840339410a0df7d3497d402283e7a30064769c9 | |
| parent | 6cfcf77573fb9714afd09b9b9ead05e002102243 (diff) | |
| download | qemu-3820602f8059dfd4034d38bb727cdbc8759631db.zip qemu-3820602f8059dfd4034d38bb727cdbc8759631db.tar.gz qemu-3820602f8059dfd4034d38bb727cdbc8759631db.tar.bz2 | |
target/riscv: Remove the hardcoded RVXLEN macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
| -rw-r--r-- | target/riscv/cpu.c | 6 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 6 |
2 files changed, 5 insertions, 7 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 04ac03f..3191fd0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -147,7 +147,11 @@ static void set_resetvec(CPURISCVState *env, target_ulong resetvec) static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#if defined(TARGET_RISCV32) + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#elif defined(TARGET_RISCV64) + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#endif set_priv_version(env, PRIV_VERSION_1_11_0); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index add734b..7e879fb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -54,12 +54,6 @@ #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) -#if defined(TARGET_RISCV32) -#define RVXLEN RV32 -#elif defined(TARGET_RISCV64) -#define RVXLEN RV64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') |