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| author | Yiting Wang <yiting.wang@windriver.com> | 2020-01-03 11:53:42 +0800 |
|---|---|---|
| committer | Michael Roth <mdroth@linux.vnet.ibm.com> | 2020-06-22 12:08:50 -0500 |
| commit | c1cad76dcd7630333738393625399b8ca0b71e43 (patch) | |
| tree | d7a038bfae992561bbcef47215eb3d68fc934492 | |
| parent | a6e44eee6c6567b1cbf0365bd95f9f199d8f2764 (diff) | |
| download | qemu-c1cad76dcd7630333738393625399b8ca0b71e43.zip qemu-c1cad76dcd7630333738393625399b8ca0b71e43.tar.gz qemu-c1cad76dcd7630333738393625399b8ca0b71e43.tar.bz2 | |
riscv: Set xPIE to 1 after xRET
When executing an xRET instruction, supposing xPP holds the
value y, xIE is set to xPIE; the privilege mode is changed to y;
xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.
Signed-off-by: Yiting Wang <yiting.wang@windriver.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
(cherry picked from commit a37f21c27d3e2342c2080aafd4cfe7e949612428)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
| -rw-r--r-- | target/riscv/op_helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 331cc36..e87c911 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -93,7 +93,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) env->priv_ver >= PRIV_VERSION_1_10_0 ? MSTATUS_SIE : MSTATUS_UIE << prev_priv, get_field(mstatus, MSTATUS_SPIE)); - mstatus = set_field(mstatus, MSTATUS_SPIE, 0); + mstatus = set_field(mstatus, MSTATUS_SPIE, 1); mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); riscv_cpu_set_mode(env, prev_priv); env->mstatus = mstatus; @@ -118,7 +118,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) env->priv_ver >= PRIV_VERSION_1_10_0 ? MSTATUS_MIE : MSTATUS_UIE << prev_priv, get_field(mstatus, MSTATUS_MPIE)); - mstatus = set_field(mstatus, MSTATUS_MPIE, 0); + mstatus = set_field(mstatus, MSTATUS_MPIE, 1); mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); riscv_cpu_set_mode(env, prev_priv); env->mstatus = mstatus; |