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| author | Peter Maydell <peter.maydell@linaro.org> | 2011-10-19 16:14:06 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2011-10-19 16:14:06 +0000 |
| commit | b8b8ea05c4008343afcedf99b9c91fd750ea90e5 (patch) | |
| tree | 4d1c4eee3a5e8ada8af69de5b4bafde58f80732e | |
| parent | 477899908fd2e6ed72faf18ef5ab09f2ae746a8a (diff) | |
| download | qemu-b8b8ea05c4008343afcedf99b9c91fd750ea90e5.zip qemu-b8b8ea05c4008343afcedf99b9c91fd750ea90e5.tar.gz qemu-b8b8ea05c4008343afcedf99b9c91fd750ea90e5.tar.bz2 | |
target-arm: Add ARM UDIV/SDIV support
Add support for UDIV and SDIV in ARM mode. This is a new optional
feature for A profile cores (Thumb mode has had UDIV and SDIV for
M profile cores for some time).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-arm/cpu.h | 1 | ||||
| -rw-r--r-- | target-arm/helper.c | 5 | ||||
| -rw-r--r-- | target-arm/translate.c | 19 |
3 files changed, 24 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 00e012e..af3904d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -375,6 +375,7 @@ enum arm_features { ARM_FEATURE_V5, ARM_FEATURE_STRONGARM, ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ + ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target-arm/helper.c b/target-arm/helper.c index faf0283..3a51fd7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -207,7 +207,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_VFP_FP16); set_feature(env, ARM_FEATURE_NEON); set_feature(env, ARM_FEATURE_THUMB2EE); - set_feature(env, ARM_FEATURE_THUMB_DIV); + set_feature(env, ARM_FEATURE_ARM_DIV); set_feature(env, ARM_FEATURE_V7MP); break; case ARM_CPUID_TI915T: @@ -261,6 +261,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); } + if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { + set_feature(env, ARM_FEATURE_THUMB_DIV); + } } void cpu_reset(CPUARMState *env) diff --git a/target-arm/translate.c b/target-arm/translate.c index deb0bcf..812a9e7 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7639,6 +7639,25 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) store_reg(s, rn, tmp); } break; + case 1: + case 3: + /* SDIV, UDIV */ + if (!arm_feature(env, ARM_FEATURE_ARM_DIV)) { + goto illegal_op; + } + if (((insn >> 5) & 7) || (rd != 15)) { + goto illegal_op; + } + tmp = load_reg(s, rm); + tmp2 = load_reg(s, rs); + if (insn & (1 << 21)) { + gen_helper_udiv(tmp, tmp, tmp2); + } else { + gen_helper_sdiv(tmp, tmp, tmp2); + } + tcg_temp_free_i32(tmp2); + store_reg(s, rn, tmp); + break; default: goto illegal_op; } |