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| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-01-03 19:05:37 +0100 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-01-24 17:48:33 +0100 |
| commit | 99e49abf119f700bf8664b7dfc60c22d9eaf9159 (patch) | |
| tree | d167652f5913f88fc59214c420335c827dc34620 | |
| parent | be3a131a057ce30038a179d718d15be9383b1258 (diff) | |
| download | qemu-99e49abf119f700bf8664b7dfc60c22d9eaf9159.zip qemu-99e49abf119f700bf8664b7dfc60c22d9eaf9159.tar.gz qemu-99e49abf119f700bf8664b7dfc60c22d9eaf9159.tar.bz2 | |
target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers
Rename macros for extracting 3-bit-coded GPR numbers, to achieve
better consistency with the nanoMIPS documentation.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| -rw-r--r-- | target/mips/translate.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 06e7bc6..2140ecd 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -18460,9 +18460,9 @@ enum { /* extraction utilities */ -#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7) -#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7) -#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7) +#define NANOMIPS_EXTRACT_RT3(op) ((op >> 7) & 0x7) +#define NANOMIPS_EXTRACT_RS3(op) ((op >> 4) & 0x7) +#define NANOMIPS_EXTRACT_RD3(op) ((op >> 1) & 0x7) #define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f) #define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f) @@ -18559,8 +18559,8 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, static void gen_pool16c_nanomips_insn(DisasContext *ctx) { - int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode)); - int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); + int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode)); + int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); switch (extract32(ctx->opcode, 2, 2)) { case NM_NOT16: @@ -21861,9 +21861,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) { uint32_t op; - int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode)); - int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); - int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode)); + int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode)); + int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); + int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode)); int offset; int imm; @@ -22026,7 +22026,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_SB16: rt = decode_gpr_gpr3_src_store( - NANOMIPS_EXTRACT_RD(ctx->opcode)); + NANOMIPS_EXTRACT_RT3(ctx->opcode)); gen_st(ctx, OPC_SB, rt, rs, offset); break; case NM_LBU16: @@ -22045,7 +22045,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_SH16: rt = decode_gpr_gpr3_src_store( - NANOMIPS_EXTRACT_RD(ctx->opcode)); + NANOMIPS_EXTRACT_RT3(ctx->opcode)); gen_st(ctx, OPC_SH, rt, rs, offset); break; case NM_LHU16: @@ -22100,14 +22100,14 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_SW16: rt = decode_gpr_gpr3_src_store( - NANOMIPS_EXTRACT_RD(ctx->opcode)); - rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); + NANOMIPS_EXTRACT_RT3(ctx->opcode)); + rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); offset = extract32(ctx->opcode, 0, 4) << 2; gen_st(ctx, OPC_SW, rt, rs, offset); break; case NM_SWGP16: rt = decode_gpr_gpr3_src_store( - NANOMIPS_EXTRACT_RD(ctx->opcode)); + NANOMIPS_EXTRACT_RT3(ctx->opcode)); offset = extract32(ctx->opcode, 0, 7) << 2; gen_st(ctx, OPC_SW, rt, 28, offset); break; |