diff options
author | Alex Bligh <alex@alex.org.uk> | 2013-08-21 16:03:04 +0100 |
---|---|---|
committer | Stefan Hajnoczi <stefanha@redhat.com> | 2013-08-22 19:14:24 +0200 |
commit | 884f17c235095af99b92dd8cd10bb824a5b0f777 (patch) | |
tree | 32ad8d364730760e3aeb4a08ae2c24e91f7fc709 | |
parent | 7bf8fbde449600926370f744b2b3d9cc819ca74f (diff) | |
download | qemu-884f17c235095af99b92dd8cd10bb824a5b0f777.zip qemu-884f17c235095af99b92dd8cd10bb824a5b0f777.tar.gz qemu-884f17c235095af99b92dd8cd10bb824a5b0f777.tar.bz2 |
aio / timers: Convert rtc_clock to be a QEMUClockType
Convert rtc_clock to be a QEMUClockType
Move rtc_clock users to use the new API
Signed-off-by: Alex Bligh <alex@alex.org.uk>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
-rw-r--r-- | hw/arm/omap1.c | 4 | ||||
-rw-r--r-- | hw/arm/pxa2xx.c | 35 | ||||
-rw-r--r-- | hw/arm/strongarm.c | 10 | ||||
-rw-r--r-- | hw/timer/m48t59.c | 4 | ||||
-rw-r--r-- | hw/timer/mc146818rtc.c | 28 | ||||
-rw-r--r-- | hw/timer/pl031.c | 13 | ||||
-rw-r--r-- | hw/timer/twl92230.c | 8 | ||||
-rw-r--r-- | include/sysemu/sysemu.h | 2 | ||||
-rw-r--r-- | target-alpha/sys_helper.c | 2 | ||||
-rw-r--r-- | vl.c | 10 |
10 files changed, 61 insertions, 55 deletions
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index b6a0b27..864c07e 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -2894,7 +2894,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s) s->pm_am = 0; s->auto_comp = 0; s->round = 0; - s->tick = qemu_get_clock_ms(rtc_clock); + s->tick = qemu_clock_get_ms(rtc_clock); memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); s->alarm_tm.tm_mday = 0x01; s->status = 1 << 7; @@ -2915,7 +2915,7 @@ static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, s->irq = timerirq; s->alarm = alarmirq; - s->clk = qemu_new_timer_ms(rtc_clock, omap_rtc_tick, s); + s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); omap_rtc_reset(s); diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 17ddd3f..331bc72 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -842,7 +842,7 @@ static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) { - int64_t rt = qemu_get_clock_ms(rtc_clock); + int64_t rt = qemu_clock_get_ms(rtc_clock); s->last_rcnr += ((rt - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); s->last_rdcr += ((rt - s->last_hz) << 15) / @@ -852,7 +852,7 @@ static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) { - int64_t rt = qemu_get_clock_ms(rtc_clock); + int64_t rt = qemu_clock_get_ms(rtc_clock); if (s->rtsr & (1 << 12)) s->last_swcr += (rt - s->last_sw) / 10; s->last_sw = rt; @@ -860,7 +860,7 @@ static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) { - int64_t rt = qemu_get_clock_ms(rtc_clock); + int64_t rt = qemu_clock_get_ms(rtc_clock); if (s->rtsr & (1 << 15)) s->last_swcr += rt - s->last_pi; s->last_pi = rt; @@ -986,16 +986,19 @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, case PIAR: return s->piar; case RCNR: - return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / - (1000 * ((s->rttr & 0xffff) + 1)); + return s->last_rcnr + + ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / + (1000 * ((s->rttr & 0xffff) + 1)); case RDCR: - return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / - (1000 * ((s->rttr & 0xffff) + 1)); + return s->last_rdcr + + ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / + (1000 * ((s->rttr & 0xffff) + 1)); case RYCR: return s->last_rycr; case SWCR: if (s->rtsr & (1 << 12)) - return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10; + return s->last_swcr + + (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; else return s->last_swcr; default: @@ -1135,14 +1138,14 @@ static int pxa2xx_rtc_init(SysBusDevice *dev) s->last_swcr = (tm.tm_hour << 19) | (tm.tm_min << 13) | (tm.tm_sec << 7); s->last_rtcpicr = 0; - s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock); - - s->rtc_hz = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); - s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); - s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); - s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); - s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); - s->rtc_pi = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); + s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); + + s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); + s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); + s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); + s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); + s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); + s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); sysbus_init_irq(dev, &s->rtc_irq); diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 7b8ef8c..6528cc0 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -269,7 +269,7 @@ static inline void strongarm_rtc_int_update(StrongARMRTCState *s) static void strongarm_rtc_hzupdate(StrongARMRTCState *s) { - int64_t rt = qemu_get_clock_ms(rtc_clock); + int64_t rt = qemu_clock_get_ms(rtc_clock); s->last_rcnr += ((rt - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); s->last_hz = rt; @@ -322,7 +322,7 @@ static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, return s->rtar; case RCNR: return s->last_rcnr + - ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / + ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); default: printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); @@ -388,10 +388,10 @@ static int strongarm_rtc_init(SysBusDevice *dev) qemu_get_timedate(&tm, 0); s->last_rcnr = (uint32_t) mktimegm(&tm); - s->last_hz = qemu_get_clock_ms(rtc_clock); + s->last_hz = qemu_clock_get_ms(rtc_clock); - s->rtc_alarm = qemu_new_timer_ms(rtc_clock, strongarm_rtc_alarm_tick, s); - s->rtc_hz = qemu_new_timer_ms(rtc_clock, strongarm_rtc_hz_tick, s); + s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); + s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); sysbus_init_irq(dev, &s->rtc_irq); sysbus_init_irq(dev, &s->rtc_hz_irq); diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c index 0cc9e5b..098e5ad 100644 --- a/hw/timer/m48t59.c +++ b/hw/timer/m48t59.c @@ -137,7 +137,7 @@ static void alarm_cb (void *opaque) /* Repeat once a second */ next_time = 1; } - qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) + + qemu_mod_timer(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) + next_time * 1000); qemu_set_irq(NVRAM->IRQ, 0); } @@ -700,7 +700,7 @@ static void m48t59_realize_common(M48t59State *s, Error **errp) { s->buffer = g_malloc0(s->size); if (s->model == 59) { - s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s); + s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s); s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); } qemu_get_timedate(&s->alarm, 0); diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c index d12f6e7..1c6bb29 100644 --- a/hw/timer/mc146818rtc.c +++ b/hw/timer/mc146818rtc.c @@ -102,7 +102,7 @@ static inline bool rtc_running(RTCState *s) static uint64_t get_guest_rtc_ns(RTCState *s) { uint64_t guest_rtc; - uint64_t guest_clock = qemu_get_clock_ns(rtc_clock); + uint64_t guest_clock = qemu_clock_get_ns(rtc_clock); guest_rtc = s->base_rtc * NSEC_PER_SEC + guest_clock - s->last_update + s->offset; @@ -117,7 +117,7 @@ static void rtc_coalesced_timer_update(RTCState *s) } else { /* divide each RTC interval to 2 - 8 smaller intervals */ int c = MIN(s->irq_coalesced, 7) + 1; - int64_t next_clock = qemu_get_clock_ns(rtc_clock) + + int64_t next_clock = qemu_clock_get_ns(rtc_clock) + muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE); qemu_mod_timer(s->coalesced_timer, next_clock); } @@ -238,7 +238,7 @@ static void check_update_timer(RTCState *s) guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC; /* if UF is clear, reprogram to next second */ - next_update_time = qemu_get_clock_ns(rtc_clock) + next_update_time = qemu_clock_get_ns(rtc_clock) + NSEC_PER_SEC - guest_nsec; /* Compute time of next alarm. One second is already accounted @@ -371,7 +371,7 @@ static void rtc_update_timer(void *opaque) rtc_update_time(s); s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; - if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) { + if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) { irqs |= REG_C_AF; if (s->cmos_data[RTC_REG_B] & REG_B_AIE) { qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC); @@ -445,7 +445,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, /* UIP bit is read only */ s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | (s->cmos_data[RTC_REG_A] & REG_A_UIP); - periodic_timer_update(s, qemu_get_clock_ns(rtc_clock)); + periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); check_update_timer(s); break; case RTC_REG_B: @@ -475,7 +475,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, qemu_irq_lower(s->irq); } s->cmos_data[RTC_REG_B] = data; - periodic_timer_update(s, qemu_get_clock_ns(rtc_clock)); + periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); check_update_timer(s); break; case RTC_REG_C: @@ -535,7 +535,7 @@ static void rtc_set_time(RTCState *s) rtc_get_time(s, &tm); s->base_rtc = mktimegm(&tm); - s->last_update = qemu_get_clock_ns(rtc_clock); + s->last_update = qemu_clock_get_ns(rtc_clock); rtc_change_mon_event(&tm); } @@ -590,7 +590,8 @@ static int update_in_progress(RTCState *s) if (timer_pending(s->update_timer)) { int64_t next_update_time = timer_expire_time_ns(s->update_timer); /* Latch UIP until the timer expires. */ - if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) { + if (qemu_clock_get_ns(rtc_clock) >= + (next_update_time - UIP_HOLD_LENGTH)) { s->cmos_data[RTC_REG_A] |= REG_A_UIP; return 1; } @@ -695,7 +696,7 @@ static void rtc_set_date_from_host(ISADevice *dev) qemu_get_timedate(&tm, 0); s->base_rtc = mktimegm(&tm); - s->last_update = qemu_get_clock_ns(rtc_clock); + s->last_update = qemu_clock_get_ns(rtc_clock); s->offset = 0; /* set the CMOS date */ @@ -843,7 +844,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp) switch (s->lost_tick_policy) { case LOST_TICK_SLEW: s->coalesced_timer = - qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s); + timer_new_ns(rtc_clock, rtc_coalesced_timer, s); break; case LOST_TICK_DISCARD: break; @@ -853,12 +854,13 @@ static void rtc_realizefn(DeviceState *dev, Error **errp) } #endif - s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s); - s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s); + s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s); + s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s); check_update_timer(s); s->clock_reset_notifier.notify = rtc_notify_clock_reset; - qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier); + qemu_clock_register_reset_notifier(QEMU_CLOCK_REALTIME, + &s->clock_reset_notifier); s->suspend_notifier.notify = rtc_notify_suspend; qemu_register_suspend_notifier(&s->suspend_notifier); diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c index d5e2f3e..e398a67 100644 --- a/hw/timer/pl031.c +++ b/hw/timer/pl031.c @@ -78,7 +78,7 @@ static void pl031_interrupt(void * opaque) static uint32_t pl031_get_count(PL031State *s) { - int64_t now = qemu_get_clock_ns(rtc_clock); + int64_t now = qemu_clock_get_ns(rtc_clock); return s->tick_offset + now / get_ticks_per_sec(); } @@ -94,7 +94,7 @@ static void pl031_set_alarm(PL031State *s) qemu_del_timer(s->timer); pl031_interrupt(s); } else { - int64_t now = qemu_get_clock_ns(rtc_clock); + int64_t now = qemu_clock_get_ns(rtc_clock); qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec()); } } @@ -201,9 +201,10 @@ static int pl031_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); qemu_get_timedate(&tm, 0); - s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec(); + s->tick_offset = mktimegm(&tm) - + qemu_clock_get_ns(rtc_clock) / get_ticks_per_sec(); - s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s); + s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s); return 0; } @@ -213,7 +214,7 @@ static void pl031_pre_save(void *opaque) /* tick_offset is base_time - rtc_clock base time. Instead, we want to * store the base time relative to the vm_clock for backwards-compatibility. */ - int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); + int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec(); } @@ -221,7 +222,7 @@ static int pl031_post_load(void *opaque, int version_id) { PL031State *s = opaque; - int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); + int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec(); pl031_set_alarm(s); return 0; diff --git a/hw/timer/twl92230.c b/hw/timer/twl92230.c index b730d85..431677e 100644 --- a/hw/timer/twl92230.c +++ b/hw/timer/twl92230.c @@ -72,14 +72,14 @@ static inline void menelaus_update(MenelausState *s) static inline void menelaus_rtc_start(MenelausState *s) { - s->rtc.next += qemu_get_clock_ms(rtc_clock); + s->rtc.next += qemu_clock_get_ms(rtc_clock); qemu_mod_timer(s->rtc.hz_tm, s->rtc.next); } static inline void menelaus_rtc_stop(MenelausState *s) { qemu_del_timer(s->rtc.hz_tm); - s->rtc.next -= qemu_get_clock_ms(rtc_clock); + s->rtc.next -= qemu_clock_get_ms(rtc_clock); if (s->rtc.next < 1) s->rtc.next = 1; } @@ -782,7 +782,7 @@ static void menelaus_pre_save(void *opaque) { MenelausState *s = opaque; /* Should be <= 1000 */ - s->rtc_next_vmstate = s->rtc.next - qemu_get_clock_ms(rtc_clock); + s->rtc_next_vmstate = s->rtc.next - qemu_clock_get_ms(rtc_clock); } static int menelaus_post_load(void *opaque, int version_id) @@ -843,7 +843,7 @@ static int twl92230_init(I2CSlave *i2c) { MenelausState *s = FROM_I2C_SLAVE(MenelausState, i2c); - s->rtc.hz_tm = qemu_new_timer_ms(rtc_clock, menelaus_rtc_hz, s); + s->rtc.hz_tm = timer_new_ms(rtc_clock, menelaus_rtc_hz, s); /* Three output pins plus one interrupt pin. */ qdev_init_gpio_out(&i2c->qdev, s->out, 4); diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index d7a77b6..b1aa059 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -124,7 +124,7 @@ extern int boot_menu; extern uint8_t *boot_splash_filedata; extern size_t boot_splash_filedata_size; extern uint8_t qemu_extra_params_fw[2]; -extern QEMUClock *rtc_clock; +extern QEMUClockType rtc_clock; #define MAX_NODES 64 #define MAX_CPUMASK_BITS 255 diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c index 97cf9eb..552100c 100644 --- a/target-alpha/sys_helper.c +++ b/target-alpha/sys_helper.c @@ -93,7 +93,7 @@ uint64_t helper_get_vmtime(void) uint64_t helper_get_walltime(void) { - return qemu_get_clock_ns(rtc_clock); + return qemu_clock_get_ns(rtc_clock); } void helper_set_alarm(CPUAlphaState *env, uint64_t expire) @@ -196,7 +196,7 @@ NICInfo nd_table[MAX_NICS]; int autostart; static int rtc_utc = 1; static int rtc_date_offset = -1; /* -1 means no change */ -QEMUClock *rtc_clock; +QEMUClockType rtc_clock; int vga_interface_type = VGA_NONE; static int full_screen = 0; static int no_frame = 0; @@ -805,11 +805,11 @@ static void configure_rtc(QemuOpts *opts) value = qemu_opt_get(opts, "clock"); if (value) { if (!strcmp(value, "host")) { - rtc_clock = host_clock; + rtc_clock = QEMU_CLOCK_HOST; } else if (!strcmp(value, "rt")) { - rtc_clock = rt_clock; + rtc_clock = QEMU_CLOCK_REALTIME; } else if (!strcmp(value, "vm")) { - rtc_clock = vm_clock; + rtc_clock = QEMU_CLOCK_VIRTUAL; } else { fprintf(stderr, "qemu: invalid option value '%s'\n", value); exit(1); @@ -2965,7 +2965,7 @@ int main(int argc, char **argv, char **envp) runstate_init(); init_clocks(); - rtc_clock = host_clock; + rtc_clock = QEMU_CLOCK_HOST; qemu_cache_utils_init(envp); |