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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-02-21 12:56:24 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-03-16 00:55:04 +0800 |
| commit | 7f34ed4bcdfda55f978f51aadca64aa970c9f4b6 (patch) | |
| tree | 9e9619a53c1d7e5b4403e702fd889b90e792b776 | |
| parent | b2e3ae9452fa55eb036739ec39c33f0782a97504 (diff) | |
| download | qemu-7f34ed4bcdfda55f978f51aadca64aa970c9f4b6.zip qemu-7f34ed4bcdfda55f978f51aadca64aa970c9f4b6.tar.gz qemu-7f34ed4bcdfda55f978f51aadca64aa970c9f4b6.tar.bz2 | |
tcg/i386: Support INDEX_op_dup2_vec for -m32
Unknown why -m32 was passing with gcc but not clang; it should have
failed for both. This would be used for tcg_gen_dup_i64_vec, and
visible with the right TB and an aarch64 guest.
Reported-by: Max Reitz <mreitz@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/i386/tcg-target.inc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index fc05909..d7e59e7 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2696,6 +2696,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_x86_packus_vec: insn = packus_insn[vece]; goto gen_simd; +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_dup2_vec: + /* Constraints have already placed both 32-bit inputs in xmm regs. */ + insn = OPC_PUNPCKLDQ; + goto gen_simd; +#endif gen_simd: tcg_debug_assert(insn != OPC_UD2); if (type == TCG_TYPE_V256) { @@ -3045,6 +3051,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_x86_vperm2i128_vec: case INDEX_op_x86_punpckl_vec: case INDEX_op_x86_punpckh_vec: +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_dup2_vec: +#endif return &x_x_x; case INDEX_op_dup_vec: case INDEX_op_shli_vec: |